【作者】 李士忠；

【导师】 马丕明；

【作者基本信息】 山东大学 ， 通信与信息系统， 2010， 硕士

【摘要】 低密度奇偶校验(LDPC)码是由Gallager于1962年提出的一种基于稀疏校验矩阵的线性分组码,具有逼近香农限的良好译码性能。LDPC码已成为多个通信标准中的纠错编码方案,因此对LDPC码编译码器的硬件实现是目前的研究热点之一。LDPC编码的主要问题是找到编码复杂度与码长成线性关系的编码方法,而译码的主要问题是找到一种译码结构实现译码复杂度、译码性能和译码器吞吐量的有效折衷。准循环LDPC (QC-LDPC)码是一类重要的LDPC码,其校验矩阵具有准循环性,在编码上可以利用反馈移位寄存器实现具有线性复杂度的编码器,译码时也大大降低了存储空间。本文从理论研究和硬件实现两个方面对QC-LDPC码进行了深入研究,并基于FPGA实现了QC-LDPC码的编、译码器的硬件设计。主要工作包括：1、针对QC-LDPC码的快速编码,实现了校验矩阵满秩时准循环校验矩阵转换到准循环生成矩阵的算法,并对校验矩阵不满秩时的转换算法进行了研究。2、基于准循环生成矩阵,研究和实现了串行编码、并行编码、两级编码三种编码算法。在两级编码的基础上,增加一级电路的复用,提出了一种新的编码器结构,提高了编码效率和运行时间。3、在对LDPC码编、译码器的计算机浮点仿真的基础上,对基于最小和算法的译码初始化和译码过程进行了定点仿真。结果表明,定点仿真的结果比浮点仿真的结果有0.3-0.5dB的性能损失,采用的定点处理算法是合理有效的。4、在ISE8.2和modelsim6.2软件平台上,运用Verilog HDL编程语言,基于译码器的部分并行结构,设计实现了QC-LDPC码的最小和算法译码。更多还原

【Abstract】 Low density parity-check (LDPC) code was proposed in 1962 by Gallager, which is a kind of linear block codes based on a sparse check matrix. its decoding performance can achieve Shannon Limit. Many communication standards have already adopted LDPC codes as the Error-Correcting codes. So, the hardware implementation of LDPC encoder and decoder are one of the research interests at present.The main problem of LDPC encoding is to find an efficient encoding algorithm with linear complexity, and the main problem of LDPC decoding is to make a trade-off between hardware complexity, performance and throughput.QC-LDPC code is an important subclass of LDPC codes. Because of the cyclic symmetry, the encoding complexity of QC-LDPC codes are linearly proportional with code length and the decoding storage space is reduced greatly. This thesis studies both the theory and hardware implementation of LDPC codes, and implements the encoder and decoder of QC-LDPC codes on FPGA. The main works are as follows:1. The algorithm from the parity-check matrix to the generator matrix is realized when the check matrix is full rank, and the case when the check matrix is not full rank is also researched.2. Three fast encoding algorithms for QC-LDPC codes are researched and realized, which are serial encoder, parallel encoder and two-stage encoder. Based on the two-stage encoder, a more effective encoding structure by reusing the first stage circuits is proposed. Simulation results show that the encoding efficiency and working frequency are improved.3. Floating simulation of the LDPC encoding and decoding system is performed and fixed simulation of the Mim-Sum decoder is completed. The results show that there are about 0.3 to 0.5 performances losses and the fixed-point processing program is reasonable and effective.4. Hardware design and implementation of partially-parallel decoder are completed on the ISE 8.2 and modelsim 6.2 software platform using Verilog HDL.更多还原