【作者】 刘宇峥；

【导师】 张玉明； 傅启攀；

【作者基本信息】 西安电子科技大学 ， 软件工程， 2010， 硕士

【摘要】 可编程逻辑块是FPGA可以通过配置实现各种数字电路结构的核心器件。其设计的优劣直接影响着FPGA实现具体设计的性能及FPGA芯片可以承载的最大系统级晶体管数。因此,在FPGA芯片设计中,可编程逻辑块的设计是最关键的环节。本文使用130nm工艺设计了一款适用于1000万系统门FPGA的可编程逻辑块。根据从顶到底的全定制设计方法,首先利用实验法及CAD工具完成了总体结构初步设计,然后根据各模块的可配置的功能特点结合可实现电路的基本形式,完成了电路的手工搭建工作,并且利用Elmore线性模型及Logic effort方法完成速度的优化及晶体管尺寸的确定,最后根据总体结构及面积的大小进行了版图规划,并对所设计的模块进行功耗评估、仿真验证、速度性能对比等。设计完成的可编程逻辑块,独有一条快速的查找表输出路径,提高了查找表独立使用时的速度,与Xilinx VirtexII相比该路径速度提升了接近10%;另外加入了一条快速进位路径,提高了FPGA实现加法器的性能;所设计的可配置存储单元可以根据配置成为同步/异步的锁存器/D触发器,提高了存储单元的多变性,并且利用低功耗工艺,使可编程逻辑块的静态电流约降低为441.46nA,从而整体降低以此模块实现的FPGA芯片的静态功耗。所设计的可编程逻辑块可实现1000万系统门的FPGA芯片,并通过MPW流片验证该模块查找表、可编程存储器、进位链等功能的正确性。更多还原

【Abstract】 Configurable logic blocks is the core of the FPGAs which makes FPGA be able to achieve a variety of digital circuit structures.The quality of the block’s design directly effects the performance of the FPGA and the maximum system gates that FPGA included. Therefore,the design of the configuration logic block is the most important thing in the design of FPGA devices.The goal of this paper is to develop a method of designing a configurable logic block , and design a configurable logic block with 130nm CMOS process which can be used to construct a 10 million system gates FPGA device.At first, the overall structure of the configurable logic block is designed by combining the experiment method and CAD tool with the top-down approach. Secondly, each module of the block is implemented regarding to their specific functionalities. Third, the speed optimization and determination of the transistor sizes are carried out using Elmore linear model and logic effort method. Finally, the overlook of the layout is drawn by the structure and the area. In the end after evaluating the power consumtion of the block we verified the functionality and performance of the block through simulations .The completed configurable logic block has a unique fast output path of the lookup table. Thus, it is 10% faster than Xilinx VirtexII when it is used indepently.The configurable logic block also has a fast carrychain increasing the performance of the adder and the configurable store unite is able to be set as a synchronous / asynchronous latch / D flip-flop, which increases the volatility of the memory cell. Moreover, by introducing the low-power process, this design reduces the static current to 441.46nA, which leads to a significant reduction to the whole static power of the FPGA device.The design can be used to construct a 10 million system gates FPGA and the function of the look-up table, programmable memory, carry chain and other modules are verified by the MPW tape.更多还原