【作者】 王祺；

【导师】 吴宁；

【作者基本信息】 南京航空航天大学 ， 电路与系统， 2009， 硕士

【摘要】 随着微电子技术的不断发展,片上系统(System-on-Chip,SoC)成为超大规模集成电路设计的主流,单个芯片上将集成成百甚至上千个IP核。SoC中所包含IP核数目的不断增多,使得以总线结构为通信基础的SoC技术面临着在性能、功耗、面积、系统可靠性和可扩展性等方面的巨大挑战。片上网络(Network-on-Chip,NoC)被公认为是片上系统IP核互连通信的有效解决方案,是SoC发展的必然趋势。论文在对片上网络关键技术研究的基础之上,着重研究面向特定应用的片上网络设计。课题完成了片上网络高层次建模,从体系结构出发,研究片上网络设计参数的改变以及不同应用任务对片上网络性能的影响,主要包括网络负载、数据通信模式、拓扑结构、交换方式四个方面。为了更精确的研究片上网络性能,进一步设计了4x4 mesh拓扑结构的RTL级片上网络与仿真验证平台,其网络接口服从开放式核协议(Open Core Protocol,OCP),提高网络的通用性。使用synopsys EDA工具完成对所设计片上网络的仿真验证和逻辑综合,通过延时、面积和功耗三项指标来分析网络性能。最后以H.264解码为实际应用,对应用进行并行性划分,映射到已设计的片上网络中,并对其功能进行验证,完成设计仿真与综合,着重给出芯片面积和功耗两项性能指标的分析结果。更多还原

【Abstract】 With the development of micro-electronics technology, SoC become mainly technique in very large scale integrated circuit, hunderds of IP cores will be intergrating in a single chip . With the growing number of IP cores in a single chip, bus based SoC are undergoing huge challenges in performance , power, area, system reliability and scalability, restrict the development of SoC.Network-on-Chip (NoC) is an emerging IC architecture that cope with the increasing complexity and communication requirements of current SoC. Based on the research of key technology in NoC design, In this paper we constructed a NoC high-level model with network simulator OPNET. Simulations and analyses were performed with different combinations of the network parameters including network topologies, router algorithms, switch techniques, traffic patterns, communication loads. Furthermore we constructed Network-on-Chip and verification platform at RTL level with the interface based Open Core Protocol. Then simulations and synthesis were performed with synopsys EDA tools. Detailed comparative analysis of the network performance and cost in terms of latency, area and power dissipation are presented.We design Application-Specific Network-on-Chip based on H.264/AVC decode Application. First the tasks were divided into some sub-modules. Each sub-module was event-driven and communicated through network. At last, we implemented IP core design of H.264/AVC decoder based NoC. Simulations and synthesis were performed. Analyses were made in term of chip area and power dissipation..更多还原