【作者】 皮代军；

【导师】 秦水介；

【作者基本信息】 贵州大学 ， 微电子学与固体电子学， 2009， 硕士

【摘要】 随着数据采集在现代工业及科学研究中的重要地位日益突出,人们对于数据采集设备的要求也不断提高。在信号测量、图像处理、音频信号处理等一些高速、高精度的测量中,都需要进行高性能数据采集。传统的设计方法的优点是:技术成熟,可选的芯片很多,设计经验积累丰富。但传统的设计方法也存在外围芯片多,PCB面积较大,可靠性相对不高;不易升级与改进:成本高;受芯片限制,设计灵活性差,可扩展性差,可靠性相对不高等缺点。传统的高速数据采集系统一般多是采用PCI或ISA作为系统的总线,这些采集系统存在不少缺点,如安装烦琐,价格昂贵,尤其是受计算机插槽数量、地址、中断资源的限制,可扩展性差等。USB是一种新式总线接口标准,具有高速、可靠、可扩展、即插即用等特点。USB2.0协议中,数据的最高传输速率提高到480Mbps,这就使通过USB实现快速传递大容量数据的外设成为现实。而FPGA芯片因其工作频率高、设计周期短、成本低廉、可重复擦写、可扩展性好、内部资源丰富可以集采集、转换及数据传输通讯于一体等优点,可解决传统设计方法中外围芯片多、不易升级和维护、设计灵活性差、扩展性不好,可靠性不高等问题。因此,本文USB和FPGA两者的优点,设计了具有较好应用前景的基于FPGA的高精度实时数据采集与传输系统。论文在阐述了系统的整体设计思路的基础上,对电路所选芯片的结构和性能进行简单的介绍。选用具有22位高分辨率的A/D转换器ADS1212作为采集转换器,由于ADS1212的精度非常高,所以要求外接电源干扰非常小,采用三级稳压的方式来为ADS1212提供稳定的电源电压。然后提出了系统的软硬件设计与实现的方法,设计出了具有22位分辨率的高精度数据采集系统。利用FPGA作为控制器,控制A/D转换、增益设置、通道选择等。利用FPGA内部的RAM设计了先入先出(FIFO)存储器,充分利用系统资源,减少了外围电路,为电路调试及制版带来了极大的方便。同时也提升了系统的采集速度和集成度,达到了实时采集的目的。系统采用Verilog语言编程,在在QUTUSⅡ7.2中完成编译和综合,并在ModelSim SE 6.1b进行了波形仿真,并给出了FPGA控制A/D转换、增益设置、通道选择、串并转换、存储器等的波形仿真图。更多还原

【Abstract】 Data acquisition plays a more and more important role in modern industry and scientific research. According to it, the requirements of data acquisition device get highly improved. High-performance data acquisition is needed in some high speed and high precision measurements when signal measurements, image manipulation and audio frequency signal process are taken. In current, high-speed acquisition modules are mostly based on PCI bus or ISA bus.But hey have obvious disadvantages such as not easy to fix, high cost and especially they are restricted to the slot number, address and interrupt resources.USB is a newly bus interface standard, which has the features of high—speed, reliability and extensibility, plug and play. According to the USB specification Rev.2.0 protocol, the rate of data transmission is up to 480Mbps,thus it becomes realizable for a peripheral equipment to transmit great-capacity data at high speed by using USB. On the other hand, FPGA is abroad used in the fields of data processing and algorithm realization owing advantage of high work frequency, short design period,lowost, unlimited re-programming.Based on the whole design idea expounded in the thesis, the structure and performance of the chips adopted in the system are described in brief. Then the method of design and implement of software and hardware is discussed. This system combined three functions of the channel selection to control and gain setting, A/D switching control, and the data buffering asynchronous FIFO by using a FPGA as the controller of a data acquisition system. Make full use of system resources, a reduction of the external circuit, and the plate for circuit debugging brought great convenience. At the same time, the system also helped improve the acquisition speed and integration, to achieve the purpose of collecting real-time. System uses the Verilog programming language, QUTUS II 7.2 in the completed and integrated compiler and ModelSim SE 6.1b for the wave simulation, and gives the FPGA control A/D conversion, gain settings, channel selection, Serial to parall conversion, memory, etc. The simulation waveform diagram.更多还原