低噪声、高PSRR LDO电压调节器的设计

【作者】 徐洪川；

【导师】 傅兴华；

【作者基本信息】 贵州大学 ， 微电子学与固体电子学， 2009， 硕士

【摘要】 低压差线性稳压器(LDO)以其高PSRR、超低噪声、微功耗和极低的成本、外围器件少等优点将在电源管理市场上占有重要的一席。它被广泛应用于汽车电子产品、便携式电子设备、通讯设备、工业和医疗设备领域。因此,开展本课题的研究具有特别重大的现实意义。本文设计了一款高电源抑制比、低噪声低压差线性稳压器芯片,它采用0.5微米CMOS工艺设计,有良好的电源抑制比(低频时超过75dB),支持较宽的输入电压范围(2.5～6V),输出电压为1.8V,在典型电流(500mA)情况下,压差为150mV。该电路主要用作对电源敏感的后级电路(如射频电路、VCO等)的电源电压。此外,芯片中还集成了过流保护电路和过热保护电路,保证电路的安全工作。基于以上技术优势,该芯片适用于手机、数码相机、mp3、mp4播放器、PDA等手提移动设备的供电模块。本文首先阐述了低压差线性稳压器的基本理论,包括基本工作原理和主要的电路指标,然后根据性能需要进行了深入的技术研究和完整的电路设计。借助设计软件Cadence对电路进行了完整的设计和仿真,给出了合理的电路数据。仿真结果表明该电路实现了设计功能,达到了预定的设计指标。最后对全文进行了总结。更多还原

【Abstract】 The low dropout (LDO) linear regulator with high PSRR, ultra low noise, micro power loss and the lowest cost, few off-chips components will be holding an important position on market of power management. It is applied broadly in automobile electronic equipments, portable communications equipments, industrial and medical fields. Therefore, it is of great important to study the low-dropout linear voltage regulator circuit.The object of this thesis is to design a high power supply rejection ratio(PSRR)、low noise low-dropout linear voltage regulator. It adopts 0.5μm CMOS process,which has the high power supply rejection ratio (more than 75dB at low frequency), wide input voltage range (2.5-6V).The output voltage is 1.8V. When the load current is 500mA, the dropout voltage is only 150mV. The circuits is primarily used to power supply of the circuit, which is sensitive to power ripple ,such as RF,VCO and so on .In addition, the thermal shutdown and current limit sub-blocks are also integrated in this chip, which guarantee the electric circuit working in safe operation area. It is used as power supply for those systems:handset,MP3 player、MP4 player、PDA, numeral camera and so on based on the above technical advantages .During circuit designing, the basic theory of LDO linear voltage regulator, including basic working principle and the main circuit parameters, is given first. Then the technique is studied and whole circuit of the IC is designed based on the performance requirement. Applying Cadence, the whole chip and its sub-block circuits are simulated and more, the reasonable electric circuit data are given. The simulation results indicate that the IC has achieved their function object.更多还原