【作者】 江猛；

【导师】 李富华；

【作者基本信息】 苏州大学 ， 集成电路工程， 2009， 硕士

【摘要】 MCU在现实生活中越来越多,人们也越来越享受MCU带来的生活上的便利。从智能家电、消费类电子、电动自行车到远程抄表、网络支付等现代化产品都体现出MCU的巨大作用和深远影响。由于MCU内核的结构不同,其工作速度和性能也不同。RISC结构简单,指令少,CISC复杂,指令较多,但编译方便;Harvard结构由于寻址方式的原因较冯·诺伊曼结构工作速度快。本文主要研究了MCU内核的电路结构和实现方式,并通过一个混合信号的MCU—HS16C711来验证内核。本文着重讨论了ALU的设计方法,演算出ALU和加法器之间的逻辑递推关系,研究分析了Core的时钟系统、时序、指令代码的译码方式、两级流水线的结构等,并设计了MCU的常用电路如RAM、Program Counter、堆栈等。本设计采用原理图直接输入的方式,利用cadence工具软件Verilog-XL进行了逻辑仿真,关键电路使用hspice进行了电路网表仿真,如四相时钟和复位电路等。设计完成后,利用QuartusII工具编译、下载,进行了FPGA测试。最后利用CSMC0.5um N阱CMOS混合信号工艺进行了版图布局和生产。通过实际流片后,验证了设计的正确性。更多还原

【Abstract】 MCU is more and more popular in our daily life . people are also increasingly brought life to enjoy the convenience of MCU. From smart home appliances, consumer electronics, electric bicycles to the remote meter reading, the MCU have acted as a important role in Internet payment and other modern products,which also has a far-reaching implications.Because of the structure of MCU core is different, its working speed and performance are also different. RISC with simple structure and less instruction,while CISC with complex structure and more instruction, but easy to compile; Harvard structure, is work faster than von Neumann as the reason of addressing modes.This paper mainly research on the MCU core circuit structure and implementation methods, and through a mixed-signal MCU - HS16C711 to verify the core. This paper is focuses on the design methods of ALU , calculuing the logic relations between the ALU and adders, researching analyzing of the Core of the clock system, timing, decoding methodv of instruction code, two pipelines structure. besides ,it also design of the MCU commonly used circuits, such as RAM, Program Counter, the stack and so on.This design uses the way of a direct schematic input , using software tool of cadence and Verilog-XL for logic simulation. The key circuits used hspice for simulation of the circuit netlist,such as Four-phase clock,circuit reset and so on . when the design was completed, I used QuartusII to compile and download, while conducted a FPGA test.At last, I used CSMC0.5um N-well CMOS mixed-signal to Carry out the territory layout and production.After passing through the actual silicon,it verify the design is correct更多还原