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0.25μm CMOS工艺中ESD关键技术研究

Key Technology of ESD in 0.25μm CMOS Process

【作者】 聂志强

【导师】 刘红侠;

【作者基本信息】 西安电子科技大学 , 微电子学与固体电子学, 2007, 硕士

【摘要】 随着集成电路的特征尺寸的缩小以及先进工艺技术的不断涌现,芯片往往会产生一些可靠性方面的问题,也使得原本具有较好性能的静电防护结构的防护能力大打折扣。在设计一款DSP(Digital Signal Processor)芯片时,为了缩短设计周期,采用了一种简单而常见的标准单元结构作为此芯片IO电路和静电防护电路。此IO标准单元能满足不同输出驱动电流的要求,但在静电防护方面却存在致命的缺陷,致使这个芯片的防护能力大幅下降。为了给该DSP芯片提供更好的静电防护,现需要对此IO标准单元结构进行优化,或采取更优秀的静电防护结构。论文研究了常见的各种ESD防护结构的同时,针对Chartered 0.25μm CMOS工艺,对原来的IO标准单元结构进行优化设计。设计方案结合了动态浮接栅耦合结构专利的优点,并实现了IO标准单元中的输出结构和静电防护结构相分离,并设计出同时具有栅耦合结构和衬底触发结构优点的静电防护单元。另外,还采用了一些关键的版图设计,有效降低了静电防护结构的触发电压和箝位电压,并获得了更好的均匀触发特性。最终的HBM模型静电放电测试结果表明,此防护结构的HBM模型的全芯片防护能力达到4kV,并已经成功应用于此款DSP芯片。

【Abstract】 As the technology scaled down, some advanced process technologies have been developed to ensure better performance, which also cause some reliability problems to chip, especially cause a strong negative effect on the robustness of electrostatic discharge protection circuit, which is used to be effective for chip.While design the input/output and ESD protection circuits of a DSP(digital signal processing) chip, a standard input/output cell, which could satisfy the different driven current requirement, is adopted to decrease the design period. While testing, this cell only bypasses lower ESD current and then fails. For increasing the ESD robustness of the DSP IC, the prior standard input/output should be optimized, or a new efficient ESD protection structure should be used. In this paper, several common ESD protection structure and Dynamic-Floating-Gate-Couple structure patent are investigated. Based on Chartered 0.25μm CMOS technology, an optimized protection circuit structure is developed, which absorb the advantage of the patent. This ESD protection structure has the advantage of both gate couple NMOS structure and substrate triggering NMOS structure, and uses a poly resistor to divide the output buffer circuit and ESD circuit to provide efficient protection for the output circuit. Some critical layout design is provided to ensure lower trigger/clamp voltage and uniform current distribution. The optimized ESD protection circuit has passed the 4kV HBM(Human Body Model) test under all test condition, and it has been applied in the DSP chip successfully.

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