【作者】 吴桂琴；

【导师】 刘岚；

【作者基本信息】 武汉理工大学 ， 电路与系统， 2009， 硕士

【摘要】 本论文讨论的是两通道数字中频接收系统的设计与实现。作为一个实现电子战关键环节的中频数字接收机,受到通信界的研究和探索的机会越来越频繁,随着信息时代和信息社会的到来,应用在中频接收机的软件无线电技术也得到了广泛的关注,通过软件无线电的算法实现不同应用功能,构造通用的、可编程的和高速数字信号处理为一体的平台是软件无线电思想的本质所在。论文用到System Generator for DSP,这是一个能实现软件无线电思想,构建软件无线电算法的软件。在这个软件环境中实现算法是本论文研究的关键。本论文的Xilinx公司系统建模工具System Generator for DSP,它在很多方面扩展了MathWorks公司的Matlab/Similink平台,在这个平台下提供了数字信号处理(DSP)建模环境,简化并加速了DSP系统级硬件设计。它通过建立数字信号处理系统的抽象算法,将抽象算法转化成可靠的硬件实现数字信号处理高层系统设计与Xilinx FPGA实现的“桥梁”。它在MATLAB/Simulink的环境下完成算法的建模,然后生成相应的工程。ISE可对工程进行仿真、综合,最后完成算法的硬件化,也可由System Generator直接生成比特流文件,并下载到FPGA。System Generator for DSP提供了系统建模级设计能力,允许在相同的环境内进行软、硬件仿真、执行和验证,DSP设计者不需要书写HDL代码,也即不熟悉HDL代码的情况下也可以使用。此外,System Generator工具还能完成高级提取,自动编译生成的FPGA代码,也可以通过低级的提取、对FPGA的低层资源进行访问,从而实现高效率FPGA设计建模。目前,基于System Generator的设计方法已在复杂系统实现中展现了强大的潜能,它必将成为未来流行的FPGA开发技术之一。本论文主要研究基于System Generator的两通道中频数字接收机。在SystemGenerator for DSP开发环境中对两个通道数字中频接收系统进行建模,两个通道分别适应0.3MHZ和3MHZ接收符号率的接收,并详细的介绍中频数字下变频的设计理论、接收系统的采样理论以及滤波抽取技术等基本概念。本文按照0.3MHZ和3MHZ下接收符号率分别设计两个滤波抽取变换方案,在System Generator环境中对两个通道的接收方案进行验证仿真,仿真最后比较结果表明方案的可行性。最后对整个中频数字化接收系统以及接收机前端的结构作了详细的介绍并加以实现,两通道系统分别可以实现从90MHZ数据率到12MHZ和1.2MHZ数据率的转变,下变频输出数据信号带宽为10MHZ的基带串行信号。论文设计实现的结论是使用System Generator for DSP建模工具可以有效地缩短设计的时间,为不熟悉HDL语言的DSP设计者提供很大的利益,搭建起DSP设计者和Xilinx FPGA的“桥梁”。更多还原

【Abstract】 This thesis discusses the design and implementation of two-channel digital intermediate frequency receiver.As a key segment of electronic warfare implementation, digital intermediate frequency receiver is investigated and evaluated by communication systems more and more frequently. In the wake of information era and information society, software radio technology applied to intermediate frequency receiver gets a lot of attention, moreover, which could implement different application functions through software radio algorithm. The essence of software radio exists in structuring a general-purpose, programmable and high speed digital signal processing platform. The software System Generator for DSP in the paper is used to implement software radio idea and structure software radio algorithm. It is critical to realize the algorithm in such software environment in the thesis.System Generator for DSP developed by Xilinx Company extends the MATLAB/Simulink platform developed by MathWorks Corporation in many aspects, which not only provides DSP modeling environment but also accelerates and simplifies the DSP system-level hardware design. Through establishing an abstract algorithm of digital signal processing systems, it achieves a "bridge" between digital signal processing systems designer and Xilinx FPGA by changing the abstract algorithm into reliable high-level hardware implementation. The designer implements an algorithm modeling in the MATLAB/Simulink environment, and then creates corresponding engineering. In ISE the designer can simulate, synthesis, and complete the hardware-oriented of an algorithm at the last. System Generator can also generate the bit-stream directly, and download to the FPGA. System Generator for DSP provides system modeling design functions, allowing simulation, emulation, running and verification, so we do not need to write HDL code, in other words, one who is not familiar with HDL code can also use it. In addition, System Generator can not only implement high-level extraction, automatic compilation, and generate code in FPGA, but also can implement lower extraction and access lower resources to achieve efficient FPGA design modeling. At present, the methods of System Generator design have already shown formidable potential in the implementation of complex system, it will become one of the popular FPGA development technologies inevitably in the near future.This design mainly studies the two-channel digital intermediate frequency receiver. Modeling the two-channel digital intermediate frequency receiving system in System Generator for DSP development environment, two channels adapt to receive symbol rate 0.3MHZ and 3MHZ respectively. The theories including the designing of DDC , the sampling of receiving systems, and the basic concepts of decimator filter technologies were introduced in details.In accordance with receiving symbol rate 0.3MHZ and 3MHZ, two filter extraction transformation programs were designed. The two-channel receiver simulation program was verified to be effective and feasible by simulation under System Generator environment. Finally, the whole digital intermediate frequency receiving system and the front-end structure of receiver were introduced in details and achieved. The data rate of the two-channel systems can transform from 90MHZ to 12MHZ and from 90MHZ to 1.2MHZ, and the output dates of DDC is a 10MHZ Base-Band Serial signal. Finally we can conclude that using System Generator for DSP modeling tools can effectively shorten the design time even if the DSP designers are not familiar with HDL language design, moreover, it provides significant benefits by building a "bridge" between the DSP designers and the Xilinx FPGA.更多还原