【作者】 胡强；

【导师】 来逢昌；

【作者基本信息】 哈尔滨工业大学 ， 微电子学与固体电子学， 2009， 硕士

【摘要】 随着无线通讯技术的发展,人们将更多的注意力转向连续时间Sigma-Delta模数转换器。连续时间结构的Sigma-Delta调制器相对于离散时间结构的Sigma-Delta调制器,具有结构精简,尺寸小,功耗低,速度高,带宽宽等特性,特别适合应用于通讯系统,是目前国内外模数转换器的研究热点之一。本文基于chart0.35μm CMOS工艺设计了一个应用于无线通讯系统中的12位低通连续时间Sigma-Delta ADC,带宽1.92MHz。连续时间Sigma-Delta ADC共分为两部分,调制器和数字滤波器。本文中调制器采用了单环三阶连续时间结构,根据系统信噪比和功耗考虑,过采样率选为16,这样在达到系统信噪比前提下,功耗较低,同时过采样率选为2的指数幂,也可以降低数字滤波器设计难度。在调制器电路实现方面,本文设计了一种高增益低噪声两级运算放大器,有效减小了运算放大器非理想性对积分器的影响。为了减小反馈DAC对系统的影响,本文特别设计了一种采用模拟校正与数字加权平均混合优化方法的反馈DAC,有效地提高了系统信噪比。同时本文还设计了一种预放大锁存的比较器构成Flash ADC型量化器,在保持较大频率的同时,减小系统功耗。本文中的数字滤波器采用了三级级联的方式,减小数字滤波器硬件消耗。降频滤波器采用了积分梳状级联(CIC)滤波器、半带滤波器和补偿滤波器级联实现。最后对滤波器进行了行为级仿真,仿真表明,降频滤波器能达到78dB信噪比和1.92MHz带宽要求。更多还原

【Abstract】 With the development of the wireless communication, people pay more and more attention to the continuous Sigma-Delta analog to digital conversion. Compared with the discrete time Sigma-Delta modulator, the continuous time Sigma-Delta modulator has the character of simple structure, small size, low power dissipation, wide bandwidth. It is very suit for the communication system and it is very popular in the research of analog to digital conversion. This paper presented a 12 bit continuous time Sigma-Delta analog to digital conversion for wireless communication bashed on chart 0.35μm CMOS process, and the ADC’s bandwidth is 1.92MHz.The continuous time Sigma-Delta ADC is consist of modulator and decimation. The continuous time modulator in this paper was adopted single loop third order structure. The over sampling ratio (OSR) was choose 16 because of the signal and noise ratio (SNR) and power dissipation. And it choose the OSR 16 can ease the difficulty of design of the decimation. In the schematic of modulator, this paper gives a high gain and low noise two-stage Opamps. The high gain and low noise Opamps can alleviate the nonideal of integrator. This paper presented a feedback DAC which was adopted analog error cancellation and digital weigh average, specially. The feedback DAC improved SNR of the modulator. And this paper presented a Flash ADC composed of pre-amplify and latch comparator. The Flash ADC can work in high clock frequency with low power dissipation. The decimation in this paper was adopted the three order cascade structure for reducing the power dissipation of the decimation. Based the theory of decimation, the decimation was implemented by cascaded of CIC filter, half band filter and compensate filter. Lastly, simulation of decimation showed that it can achieve 78dB SNR and 1.92MHz bandwidth.更多还原