【作者】 李迎盼；

【导师】 田日才；

【作者基本信息】 哈尔滨工业大学 ， 信息与通信工程， 2009， 硕士

【摘要】 双星定位系统是我国自主研制开发的区域性有源卫星导航定位系统,可全天候提供快速定位、实时导航、简短通信和精确授时四大功能。目前,该系统已初具规模,在军用和民用导航方面的发挥着日益重要的作用。近年来,随着微电子技术的进步,大规模逻辑器件的性价比不断提高,使得在单片大规模逻辑器件上实现系统级设计已经成为可能。SOPC技术是Altera公司于2000年提出的一种软硬件协同设计方案,它以IP核为基础,将处理器、存储器、定时器等系统所需要的功能模块都集成到单片FPGA上,构成可编程的片上系统。SOPC技术是一种灵活、高效的SOC解决方案,使得电路设计在设计周期、开发成本、电路规模、功耗、可靠性和硬件升级等多方面达到最优化,代表了嵌入式系统设计的发展方向。本文根据某车载型双星定位用户机的多芯片(MCU+DSP+FPGA)设计结构,本着将尽可能多的功能模块集中在FPGA中实现的设计思想,提出基于SOPC技术的单芯片实现方案。改进后,FPGA实现的功能除了原有的多通道同步扩频解调外,还包含了DSP和MCU的功能。此外,原方案中在射频部分实现的下变频、成形滤波、BPSK调制也都放入FPGA中进行数字实现。本文采用Altera提供的SOPC设计工具,从IP核的具体应用方面展开研究,完成双星定位用户机方案的实现。具体工作:接收部分完成了正交数字下变频、解扩解调、帧同步、VIterbi译码;发射部分完成了卷积编码、成形滤波和BPSK调制;而原方案中用于控制的MCU芯片,则使用SOPC Builder工具完成了NiosⅡ软核方案的微控制器设计,并移植了μC/OS-ⅡRTOS。原方案中在FPGA实现的载波和伪码同步,以及MCU软件设计,在改进方案中予以保留。限于篇幅,本文不进行讨论。更多还原

【Abstract】 Double-star positioning system, the independent research and development of China’s active regional satellite navigation and positioning system, can provide four major functions: rapid positioning, real-time navigation, shortness communication and precision. At present, the system has begun to take shape, and played an increasingly important role in the military and civilian navigation.Recently, with the development of microelectronics technology, performance price ratio of large-scale logic devices improved. System-level design in a single logic device has become possible. SOPC, put forward by Altera in 2000, is a new hardware-software co-design technology. Processor, memory, timers and other function modules needed are integrated into a FPGA based on IP core. SOPC is a flexible, cost-effective solution of SOC, making circuit design in the design cycle, development costs, circuit size, power consumption, reliability, and hardware upgrades, etc. achieve optimized. It can be predicted, SOPC technology will be embedded system design trends.This paper, based on dual-satellite positioning Vehicle terminal’s multi-chip design structure put forward a modified single-chip realization. After improvements, FPGA realizated not only multi-channel synchronous demodulator in original program, but also includes DSP and MCU functionality. In addition, DDC, shaping filter, BPSK modulation which achieved in the RF of original program is also achieved in the FPGA. In this paper, using SOPC design tools, the simulation realization of the SOPC program was completed. Receiving part: DDC, demodulation dispreading, frame synchronization and Viterbi decoding was completed. Launching part: convolution code, BPSK modulation and shaping filter were completed. SOPC Builder tool was used to complete a NiosⅡsoft-core microcontroller was completed to replace MCU chip which used to be controller in the original program. what’s more, transplantation ofμC/OS-ⅡRTOS was completed. The original program in the FPGA to achieve the carrier and PN code synchronization, as well as MCU software design, wad retained in the improvement program. Due to space limitations, do not discuss in this article.更多还原