【作者】 王波；

【导师】 金西；

【作者基本信息】 中国科学技术大学 ， 微电子学与固体电子学， 2009， 硕士

【摘要】 Reed-Solomon (RS)纠错码是目前最有效、应用最广泛的差错控制编码之一。它主要应用于数字信号的传输和存储中。由于数字信号在传输过程当中,可能受到各种干扰及信道传输特性不理想的影响使得信号发生错误,从而接收到错误的信息。近年来,人们对高速数字系统稳定性和可靠性的要求越来越高,因此纠错编码在数字信号的传输和存储中的作用也越来越重要。对纠错码的研究从上世纪50年代开始一直延续到现在。RS纠错码是移动通信系统、深空通信、数字卫星电视、磁记录系统等方面常用编码,因此对RS纠错码的研究具有重要的实际意义。如何提高编译码速度及纠错能力显得尤其重要。RS码是一种特殊的线性分组码,它的编码技术经过几十年的发展已经比较成熟。部分RS码已基于ASIC实现并得到应用,鉴于设计专用集成电路价格高昂以及灵活性欠佳,本文研究设计基于FPGA实现RS[204,188]编解码器,并考虑将此RS码应用于战术数据链传输中。由于战术数据链应用于军事海陆空三军通信中,因此对传输速率,信号可靠性要求都很高。本文中采用合理的算法,选择合适的码长以及纠错能力t,以达到适用于战术数据链,提高增强数据信息量,运行速度,降低误码率的目的。战术数据链具有实时性、可靠性、安全性等特点。实时性要求提高数据传输的速率,缩短各种机动目标信息的更新周期,可靠性即传输数据真实可靠。本文根据战术数据链的特点设计快速长RS码编译码的实现,并提高传输数据的信息量。RS码的实现分为编码和译码两个的部分,也是难点所在,编译码的运算速度直接影响数据链的传输。所以本论文主要是围绕这两点展开。论文第一章RS的应用背景以及战术数据链的相关知识。第二章和第三章主要介绍纠错码编译码理论,其中涉及到比较多的代数理论,这些理论基础是实现RS码的必要知识,在这里都作了简要的介绍。RS码的译码比较复杂,第四章专门对RS译码方法做阐释,并通过比较选择快速的译码算法。第五章介绍FPGA设计流程以及RS编译码的FPGA实现。第六章完成仿真及验证。更多还原

【Abstract】 Reed-Solomon (RS) error-correcting code is the most effective and most widely used one of the error-correcting codes. It is mainly used on digital signal transmission and storage. As the digital signal in the transmission process, there may be subject to a variety of interference and transmission characteristics of the impact of non-ideal signal makes errors, which makes people receive the wrong messages. In recent years, high-speed stability and reliability of digital systems has become increasingly demanding, so error-correcting code in digital signal transmission and storage in the increasingly act as an important role. Research on error-correcting code from the last century, the beginning of the 50’s until now, RS error-correcting code is a mobile communication system, deep space communications, digital satellite TV, magnetic recording systems commonly used codes, error-correcting code on the study of RS has important practical significance. How to improve error correction encoding and decoding speed and capacity are particularly important.RS code is a special kind of linear block codes, and its coding technology after decades of development has been more mature. RS code has the use of certain ASIC and application to achieve, given the high cost of ASIC design, as well as poor flexibility, the paper design FPGA-based realization of RS [204,188] codes. And consider the RS code used in Tactical Data Link transmission. Applies as a result of tactical data link communications in the military armed forces, and therefore transfer rate, high signal reliability requirements. In this paper, the use of a reasonable algorithm, select the appropriate error correction code length, as well as the capacity of t, in order to apply to tactical data links to improve the speed, the purpose of reducing error rate.Tactical Data Link has its own Features, such as real-time, reliability, security and so on. Real-time data is transmission to increase the rate and shorten the range the target information update cycle time, reliability data that is reliable and true. In this paper, the tactical data link in accordance with the characteristics of the design of fast long RS code of the codec to achieve and enhance the amount of information data.The first chapter of the thesis the application of RS codes background and tactical data link. Chapters II and III introduces the theory of error-correcting code encoding and decoding, which involve a relatively large number of algebraic theories, these theories are based on RS codes achieve the necessary knowledge, here are a brief introduction. Decoding RS codes is rather complicated, the fourth chapter is dedicated to the interpretation of RS decoding methods, and by comparing the choice of a fast decoding algorithm. The fifth chapter is devoted to FPGA design flow and FPGA realization of the RS codec. Chapter VI completes simulation and verification.更多还原