【作者】 黄召军；

【导师】 张树丹；

【作者基本信息】 江南大学 ， 微电子学与固体电子学， 2009， 硕士

【摘要】 随着集成电路设计和工艺水平的不断提高,集成电路的工作频率也越来越高,并且高性能、低成本仍旧是集成电路设计的主要挑战。由于直接生成高质量的高频时钟十分困难,因此,一般采用锁相环频率合成器来倍频,这样人们就可以用目前可以产生的质量非常高的低频时钟信号的晶体振荡器来生成高频信号。而其中采用最多的就是电荷泵锁相环频率合成器,它具有易于集成、低功耗、低抖动、频率牵引范围大和静态相位误差小等优点,成为了倍频信号产品的主流。本文设计了一款可实现快速锁定的三阶电荷泵锁相环频率合成器。文章在深入分析电荷泵锁相环频率合成器设计理论的基础上,根据直接数字频率合成器(DDS)的要求确定了锁相环的总体电路结构和各项性能参数。首先利用Verilog-A语言对所设计的电荷泵锁相环频率合成器进行建模,验证了快速锁定理论并对各个参数进行了优化,然后将各项参数指标分到各个模块上,进行单元电路的设计。在单元电路设计的过程中,论文重点讨论并解决了下述问题:1)电荷泵锁相环频率合成器快速理论的研究,并根据该理论建立了Verilog-A模型;2)采用含有TSPC结构的鉴频鉴相器,增大了其工作频率;3)采用了可实现自举的电荷泵结构,消除电荷共享效应,同时电荷泵控制开关采用了传输门,降低了时钟馈通和电荷注入的影响;4)压控振荡器采用四个四级延迟单元的环形振荡器,降低了压控振荡器的控制电压范围和锁定时间。同时也增大了输出频率范围,降低了压控振荡器增益,从而降低了纹波对压控振荡器输出信号的影响。5)采用动态逻辑电路来设计可编程分频器,在尽可能增大其工作频率的同时,也实现了调节范围为16～127调节要求。6)本文设计了锁定检测电路,在锁定信号坚持30个参考频率周期后,才认为电荷泵锁相环频率合成器真正实现了锁定,然后输出一个锁定指示信号。本论文中设计的电荷泵锁相环频率合成器采用SMIC 0.18μm CMOS工艺,1.8V电源供电。仿真结果表明,电荷泵锁相环频率合成器输出频率范围可实现160MHz～1.27GHz范围变化,锁定时间很短,在1us至3us之间。在VCO输出频率为160MHz时,环路的锁定时间为2.15us,抖动的峰峰值小于136ps。更多还原

【Abstract】 With the rapid development of the IC design and process, the working frequency of IC chips is more and more high. High performance and low cost are also the main challenge for chips. It is very difficult to generate high frequency signal with high performance. So we usually choose PLL(Phase-locked loop) Frequency Synthesizer to multiple the working frequency. Crystal oscillate can work with high performance frequency but its working frequency is very low. To get high performance and high frequency clock signal, we can use PLL Frequency Synthesizer and crystal oscillate. CPPLL(Charge-pump Phase-locked loop) Frequency Synthesizer is the most popular. Because of the merit of integrated easily, low power, low jitter, small phase difference error and big capture scale, the CPPLL Frequency Synthesizer has become one of the major frequency-multiple product.This paper presents a fast-locking third-order CPPLL Frequency Synthesizer. Based on the analysis of the theory of CPPLL Frequency Synthesizer and application requirements for the DDS, the structure and the performance specifications of the CPPLL Frequency Synthesizer are defined. At first, this paper built the model of the CPPLL Frequency Synthesizer in the Verilog-A language. This validate the fast-locking theory and optimize all the parameters. And then the paper design all the subcircuits with these parameters.During these procedures, the paper discusses and solves the following problems:1) researches the fast-locking theory of CPPLL Frequency Synthesizer and designs the model of CPPLL Frequency Synthesizer.2) Optimizes the Phase and Frequency Detector with TSPC structure to increase its working frequency.3) Adopts a bootstrapping CP(Charge-Pump) to solve the effect of charge sharing. The paper use the transmit gate as the CP’s switch that reduce the influence of the clock feedthrough and charge injection mismatch.4) Adopts four ring VCO and each is consist of four delay elements. It reduces the control voltage range and the locking time. It also increases the output frequency range and reduces VCO gain and reduce the effect ripple voltage to the output signal.5) Designs a programmable frequency divider with dynamic logic structure. It is possible to make the divider work in higher frequency. The divider ratio is range from 16 to 127 and this meet the design’s need.6) Adopts a type of lock-detector circuit. After the circuit locked for 30 reference frequency periods, it output a locking signal.The CPPLL Frequency Synthesizer is design in SMIC 0.18um CMOS process 1.8V supply voltage. Simulation results show that the CPPLL Frequency Synthesizer output frequency can range from 160MHz to 1270MHz. And its locking time is very little(about range from 1us to 3us). When the output of VCO is 160MHz, the lock time of the CPPLL Frequency Synthesizer is 2.15μs and the peak-to-peak jitter is less than 136ps.更多还原