【作者】 方炜园；

【导师】 陈亚光；

【作者基本信息】 中南民族大学 ， 生物医学工程， 2009， 硕士

【摘要】 脑电检测是了解脑功能状况、辅助诊断脑疾病、评估各种治疗方法的重要手段。利用常规脑电设备进行检测,由于时间和环境的限制,往往得不到有确切意义的结果。为此,人们一直致力于在非医院环境中进行长程脑电检测的动态脑电系统(AEEG)的研制工作。SOPC系统是一种基于FPGA的灵活、高效的SOC解决方案,是一种软硬件协同设计的系统设计技术。它将处理器、存储器、I/O口等系统设计需要的功能模块集成到一个可编程器件上,构成一个可编程的片上系统。SOPC是未来半导体的发展趋势。本论文设计了一个基于SOPC的脑电信号采集系统。由头皮电极采集脑电信号,并对其进行放大、滤波等预处理,再经过一个多通道模/数转换器,将其转换为数字信号。为了完成各项控制、数字滤波和数据存储,我们定制了一个SOPC系统。最终将处理过的数据保存在SD卡中供计算机进一步分析。本系统的硬件平台为DE2开发板,软件部分以NiosⅡ软核处理器为核心。功能模块以IP核的形式添加到系统中,Altera为大部分通用接口提供了IP核,因此开发周期短,调试方便,体现了SOPC的灵活高效优势。该设计主要从以下四个方面展开。对头皮电极采集的脑电信号进行了放大、滤波等预处理,以便开展后续的数字处理和存储工作。其二,利用SOPC开发工具实现了对模/数转换器的控制,编制了相应的硬件描述语言程序。其三,利用Matlab/DSP Builder进行DSP模块的设计,实现基于NiosⅡ32位CPU核的脑电信号数字FIR滤波器功能。其四,进行了FPGA外围接口的设计,包括ADC、SD卡、SDRAM等。由于SOPC系统具有的可剪裁、调试方便、开发周期短的优势,在日后的工作中,可以再对这个系统进行扩展,添加多种功能模块,如网络和无限通讯模块,为远程医疗、家庭监护系统提供了一个新的技术方案。更多还原

【Abstract】 EEG detection is an important method to know the brain status, assist in diagnosing brain disease, and evaluate therapy plan. Because of the time and environment constraints, using conventional EEG equipment to detect EEG signals often do not get the significative results in clinic. For this reason, researchers has been developing ambulatory electroencephalography system (AEEGs).SOPC system is a flexible, efficient SOC solution based on FPGA, which is a system techniques co-design hardware and software. SOPC is the trend of semiconductor development. Functional modules such as processor, memory, I / O interfaces and so on are integrated into a programmable device,to compose a programmable SOC.In this paper, we introduce a design scheme of AEEGS based on SOPC, EEG signals from scalp are amplified and filtered, and than convert EEG from analog signal to digital signal by means of a multi-channel ADC. We customize a SOPC system to create functional control signals, complete digital filtering and data storage in a SD card. We use DE2 development board as the hardware platform of the system, NiosⅡsoft-core as the processor in software part. Functional modules are integrated in the system in form of IP core. Altera provides common interface for most of the IP core, therefore, it costs a short development cycle, possesses the advantages of debugging convenience, flexibility and efficiency . The development is primarily unfolded by the following four aspects: first, we design amplifier and filter; Second, customize a SOPC system to create functional control signals, complete digital filtering and data storage; Third, design DSP module by use of Matlab / DSP Builder to realize FIR digital filter function of EEG based on NiosⅡ32 bit CPU core; Fourth, design the external interfaces of the FPGA, including the ADC, SD Card, SDRAM, etc.Due to the advantages of cutting resistance, debugging convenience and short development cycle, in the future work, SOPC system could be extended, added multiple functional modules such as network and wireless communication modules. This provides a new technology solution for telemedicion and telecare as a family monitor system.更多还原