【作者】 陈溶波；

【导师】 刘肃；

【作者基本信息】 兰州大学 ， 微电子学与固体电子学， 2009， 硕士

【摘要】 过去十多年里,数字视频技术被广泛地应用于计算机、通信、广播和电视领域,带来了电视会议、可视电话、数字电视等一系列新型应用。近些年,随着数字音视频编解码技术和超大规模集成电路的发展,以AVS和H.264/AVC为代表的新一代视频编码标准成为主流。AVS和H.264/AVC视频编码标准采用了最新的视频编码技术,获得了很好的效果,但是其压缩效率的提高是以压缩算法复杂度的提高为代价的。这使得单纯用软件来实现解码,难以达到实时,尤其是高清晰度电视,必须通过硬件电路加速解码才能实现高清实时,综合考虑,专用集成电路(ASIC)设计是解码器的最佳实现方案。本文通过研究AVS和H.264/AVC视频编解码标准,归纳了两种标准中视频编解码算法的异同点,说明了两种标准复用的可行性。在此基础上,通过软硬件的划分方法提出了一种同时支持AVS和H.264/AVC的视频解码器系统设计方案,并通过并行设计和数据流驱动等先进设计方法上对解码器硬件模块进行了合理的划分。本文对AVS和H.264/AVC多标准可配置的视频解码器的研究,有助于我国AVS高清视频编解码芯片的开发,并且有助于AVS标准产业化。为了进一步在多个领域推广AVS标准,并提高多模解码器的灵活性,本文还对解码器的输出模块(Display Feeder,DF)做了深入的研究,进而提出了DF多路并行输出的硬件结构,这种结构采用高效的片外帧缓存和片上三级缓存的方法,使得片外存储器数据带宽减少25%且数据读取速率提高将近三倍,解码器可以输出多个图像给一个监视器,还可以输出多个图像给多个监视器显示。本设计通过Verilog HDL语言加以实现,通过了Modelsim的仿真,并在FPGA上通过了验证,通过高清电视的直观显示,可以证明本设计的正确性,并说明多模视频解码器还可以进一步应用到数字视频监控领域。更多还原

【Abstract】 In the past ten years,digital video technology has been widely used in field of computer,communication,TV,broadcast,which has brought a series of new applications such as TV conference,videophone,digital TV and so on.In recent years, with the development of digital audio video codec technique and VLSI,AVS and H.264/AVC have represented a new generation of video coding standard and become to be the mainstream.By introducing the latest video coding technology,AVS and H.264/AVC gain a wonderful coding efficiency.However,the improvement of compression efficiency is based on the cost of the complexity of compression algorithm.For high-definition television,it is difficult to achieve real-time by software decoding.That makes it is difficult to achieve real-time decoding only by software.Especially high-definition television,hardware accelerator or appropriative hardware decoding circuit is necessary.Considering above situation,ASIC implementation is the best program for decoder design.By investigating AVS and H.264/AVC standards,similarities and differences about algorithm of two standards are summarized in the thesis.Furthermore,system design scheme of multi-mode decoder is proposed through the way of Hardware/Software Partitioning,and reasonable hardware modules partitioning is carried out through the way of advanced design methods,such as parallel design,data drive technique and so on.The research on multi-standard and configurable video decoder is helpful for the design of AVS SDTV/HDTV video codec chip and for the industrialization of AVS standard consequently.In order to improve decoder flexibility and promote AVS standards to more fields, the thesis also makes a deep research on decoder output module DF and proposes the hardware architecture for multi-channel parallel output.This architecture adopts an efficient method for multi-channel parallel frame buffer and three-level buffer-on-chip,which can reduce 25%of memory data bandwidth and improve nearly three times of reading speed.The decoder can output a number of pictures onto a monitor,or onto several monitors.DF design is implemented by Verilog HDL, simulated by Modelsim and successfully verified on Altera FPGA verification board. The multi-channel pictures are displayed on the high-definition television can prove this design functional correctness.So the multi-mode decoder with new DF design can be applied to the field of digital video monitor.更多还原