掺氮氧化硅栅介质对0.13um CMOS器件1/f噪声特性影响的研究

【作者】 陆肇勇；

【导师】 李炳宗；

【作者基本信息】 复旦大学 ， 集成电路工程， 2009， 硕士

【摘要】 当CMOS工艺发展到深亚微米阶段,传统的二氧化硅栅氧介质已经接近其物理极限。为减少栅氧化层的隧穿电流,提高其对硼的阻挡能力,势必要引入新的栅介质材料。在0.15μm至0.065μm的CMOS工艺中,通常的做法是在氧化层中掺氮。氮的掺入会提高栅介质的介电常数,缓解短沟器件对栅氧化层减薄的依赖,降低栅介质的隧穿电流,提高其对硼的阻挡能力。但是,传统的掺氮方法是在热氧化后通过高温氮化退火实现,氮掺杂在Si-SiO₂界面。由于氮在界面的引入改变了界面附近的晶格结构,使CMOS器件某些性能出现退化,其中特别值得注意的是,氮在界面的掺杂降低了器件的某些可靠性,增加了器件的1/f噪声（flicker noise,也叫闪烁噪声）,这对低频应用的模拟器件尤其不利。通常认为CMOS器件的1/f噪声来自沟道中载流子密度或迁移率的不规则变化,前者取决于Si-SiO₂界面态密度及其在禁带能级中的位置,后者则由载流子与声子群的散射决定。本文探讨了不同氮化及退火条件生成的掺氮氧化硅栅介质对0.13μm CMOS器件1/f噪声特性的影响。通过在线测试掺氮氧化层界面陷阱密度、氧化层总电荷、氧化层可移动电荷、氮浓度及其分布等,分析氮在氧化层中的掺杂分布对氧化层特性及作为栅介质时对CMOS器件1/f噪声特性的影响。在线监控表明,氮在Si-SiO₂界面的掺杂增加了氧化层的总电荷,在相同的退火条件下,氮的掺杂浓度越高,或其分布越靠近界面,则氧化层总电荷越高。而CMOS器件的1/f噪声测试结果表明,氮在Si-SiO₂界面的掺杂是0.13μm掺氮氧化硅栅介质CMOS器件1/f噪声特性恶化的主要原因。其机理可能是氮在界面的引入使Si-N键替代了扭曲的Si-O键,释放了过渡氧化层的应力,改变了界面附近的硅衬底的晶格结构,增强了载流子与由晶格结构决定的声子群的散射,导致CMOS器件的1/f噪声恶化。通过先氮化后氧化等方法,可将氮掺杂由Si-SiO2界面提升到SiO₂表面附近,降低氮掺杂对Si-SiO₂界面应力的影响,该方法将0.13μm CMOS器件的1/f噪声降低了14～20dB。在进行CMOS掺氮栅氧化工艺开发时,可设计不同的掺氮工艺条件,通过在线监控氧化层总电荷的方法,选择较优的栅氧化工艺来降低器件的1/f噪声,缩短工艺开发周期和成本。更多还原

【Abstract】 With the development of CMOS technology in the deep sub-micro region, the traditional silicon dioxide gate dielectric is approaching to its physical limits.To reduce the gate oxide direct tunneling current and improve its ability to prevent boron penetration,it is bound to introduce new material.For 0.15μm to 0.065μm CMOS process,the traditional method is to use nitrogen-doped silicon oxide as gate dielectric.The incorporation of nitrogen will increase the gate dielectric constant,reduce short-channel devices on the gate oxide thinning dependence and gate direct tunneling current,improve gate dielectric anti-boron penetration ability.However,the traditional nitrogen-doped method uses nitrogen gas annealing at high temperature after silicon thermal oxidation,the doped nitrogen locates near the Si-SiO₂ interface.Because it changes the lattice structure near the silicon surface,some of the CMOS devices parameters show degradation. Especially,the nitrogen doping at the interface reduces part of device’s reliability,and increases the device 1/f noise,which is especially detrimental to low-frequency analog applications.It is generally believed that CMOS 1/f noise is originated from the channel carrier density fluctuation or mobility fluctuation.The carrier density fluctuation depends on the Si-SiO₂ interface trap density and its energy in the band gap.The mobility fluctuation depends on the carriers scattering by phonon population.This thesis investigates different nitrogen-doped and anneal process gate dielectric impacts on 0.13μm CMOS 1/f noise.The dielectric’s character is studied by testing the interface trap density,oxide total charge,oxide mobile charge,nitrogen concentration and its distribution profile.Then nitrogen-doped gate dielectric impact on CMOS 1/f noise is explored.Online monitor data shows that the nitrogen at the Si-SiO₂ interface increases the oxide total charge.In the same annealing condition,if the nitrogen-doped concentration is higher,or its distribution is more close to the interface,the oxide total charge will increase.The 1/f noise test results show that the gate dielectric with nitrogen at the Si-SiO₂ interface has significant impact on 0.13μm CMOS device 1/f noise.Its mechanism could be that the Si-N bond replaces the distorted Si-0 bond at Si-SiO₂ interface,and reduces the structural transition layer’s stress,then changes the substrate surface lattice structure,enhances the carriers scattering by phonon population,and results in CMOS devices 1/f noise deterioration.A pre-nitrogen-doped process could change the nitrogen distribution from Si-SiO₂ interface to be near SiO₂ surface,which reduces 0.13μm CMOS device 1/f noise by 14～20dB.In nitrogen-doped gate dielectric process development,an online monitor of oxide total charge method could help on developing and selecting an optimized gate oxide process condition to improve the CMOS device 1/f noise,shortening the process development cycle and cost.更多还原