【作者】 隋晓锋；

【导师】 甄国涌； 焦新泉；

【作者基本信息】 中北大学 ， 微电子学与固体电子学， 2009， 硕士

【摘要】 文章通过对通用化测试台系统功能指标进行分析,从数字量输入模块方案论证、硬件设计、软件设计、可靠性、通用化设计等几方面,提出了数字量输入模块的设计方案。数字量输入模块,是通用化测试台的一部分,主要功能是接收PCM码流和CAN总线数据,并将编帧后的信号数据通过LVDS背板总线经USB接口上传给上位机,上位机经解包处理后显示信号相应的状态进行判断。论文围绕着LVDS总线技术实现、同步时钟和异步时钟PCM解码、CAN总线节点设计、模块通用化设计等关键技术展开,另外,文章还结合干扰问题提出了信号的各种抗干扰措施,包括电源抗干扰设计、PCB板布局抗干扰设计、中心控制逻辑的抗干扰设计和系统软件的抗干扰设计等。模块采用FPGA作为中心逻辑控制器,LVDS总线接口和CAN总线接口进行数据传输,具有很强的通用性和可扩展性。文章的重点具体概括为:1、数字量输入模块LVDS串行总线接口实现及上位机命令和数据经模块LVDS接口串并转化后在FPGA中的解析实现2、同步时钟和异步时钟的PCM码流在FPGA中的解码实现及产生PCM码模拟数据源的实现3、数字量输入模块CAN总线节点的设计与实现并给出了上位机对CAN节点的配置实现4、数字量输入模块通用化设计文章最后对数字量输入模块PCM自适应解码,CAN总线错误时的实时显示等仍需提高的地方提出了作者的几点想法。更多还原

【Abstract】 Digital signal input module,the part in General Test equipment,mainly transmit PCM data and CAN bus data through LVDS back plant and USB interface into PC. PC would introduce the transmitted data,show signal state and the signal information.The thesis gives the function analysis of the General Test equipment and the scheme of the digital signal transmission module,refers to scheme practice test, hardware choice,software program,universality and extensity.The thesis concentrates in the LVDS bus,PCM decoding,CAN bus key technology.In addition, the paper combine anti-jamming question and put forward various kinds of anti-jamming measurements to the system.It includes electrical source design,PCB board arrangement,central control logic design and the anti-jamming design of software,etc.The module takes FPGA as the central controller,LVDS bus and CAN bus as transmitter interface with strong universality and extensity.The important and difficult problems that was faced is analyzed adequately when I was design and debugging,at the same time it was demonstrated and explained as the important.It was generalized as follows:1、the LVDS bus interface technology application2、PCM decoding design in FPGA.3、data transmission in the CAN bus4、universality designFinally,the thesis offers some thoughts on the digital signal input module with the need to be changed.更多还原