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低功耗高性能采样保持电路的研究与设计
【作者】 樊琦；
【导师】 于奇；
【作者基本信息】 电子科技大学 ， 微电子学与固体电子学， 2009， 硕士
【摘要】 近年来,随着通信系统和消费类电子设备的发展,作为VLSI数字信号处理系统中重要模块的模/数转换器(ADC)在制造工艺、结构、性能上都有了很大的进步,正在朝着低压、低功耗、高速和高分辨率的方向发展。采样/保持电路(S/H)作为ADC中的关键单元电路,其线性度、功耗、速度和精度将直接影响到ADC系统的指标。本文分别从S/H架构、采样开关及其误差、S/H和运算放大器优化设计和S/H版图设计技术等方面研究和探讨了相关理论和相应的电路实现途径,同时基于中芯国际1.8V 0.18μm混合信号CMOS工艺,完成了12bit、100MSample/s (100MSPS)的S/H电路的设计仿真和版图绘制。文章主要内容和结果包括:1)系统分析和对比了各种S/H电路结构,针对12bit采样精度和100MHz采样速度的指标要求,选取基于开关电容技术的电容翻转型闭环S/H电路结构,以保证S/H电路设计的可行性和可靠性;2)分别建立了单管采样开关和栅压自举采样开关的等效电路模型,分析了开关的电荷注入、非线性导通电阻和采样时刻不确定性等非理想因素。针对简化S/H电路中,两种开关的非线性导通电阻引入的谐波分量进行了细致地分析和推导,并进行了Matlab仿真。在此基础上,设计了一种双边栅压自举CMOS采样开关;3)对电容翻转型S/H电路的保持态建立行为进行了深入的数学建模,系统分析了影响S/H电路大信号建立行为和小信号建立行为的各种因素,推导了S/H的总建立时间与负载电容、反馈系数、运放极点、偏置电流、信号摆幅和建立精度之间的关系式。按总建立时间小于3ns的要求,计算出运算放大器的偏置电流。运算放大器采用增益增强型折叠共源共栅结构,按照最小建立时间(MST)的要求推算了所需的增益、单位增益带宽和相位裕度等指标;4)基于SMIC 1.8V 0.18μm数模混合标准CMOS工艺,采用Hspice设计仿真了满足12bit、100MSPS要求的电容翻转型S/H电路,并采用Virtuso完成了S/H电路版图的绘制。
【Abstract】 Nowadays, along the increasing market of telecommunication systems and consumer electronic appliances, the Analog-to-Digital converters (ADCs), which are of great importance in modern VLSI digital signal processing systems, have got great development in process, architecture and performance, and are developing towards higher sampling rate, higher resolution, and lower power consumption. As the key cell of ADCs, the linearity, power consumption, speed, and resolution of the sample and hold (S/H) circuit affect the performance of the whole ADC directly.This thesis studies the academic models and corresponding circuit implementations for high speed, high resolution S/H circuits. They cover the S/H architectures, sampling switches with error sources, optimization on settling features of S/H, and layout-drawing technical. Finally, a 12bit 100MSample/s S/H circuit is designed based on SMIC 1.8V 0.18μm mixed-signal CMOS process. The details include:1) The main architectures of S/H circuits are discussed, and it specifies that the switched-capacitor close-loop flip-over S/H topology can achieve 12bit 100MSample/s performance under sufficient feasibility and reliability.2) .Equivalence circuit models are established for the single MOS switch and the bootstrapped switch, with studying on the nonideals of them, such as charge injection, nonlinear analog bandwidth and sampling moment uncertainty. For the simple S/H circuit, the harmonic, which is introduced by the nonlinear conducting resistance of two kinds of switches, is analyzed and deduced carefully. And a double-side bootstrapped CMOS switch is designed, in which buck-effect is reduced.3) Mathematic model of the flip-over S/H circuit is established, which studied the factors affecting the large-signal settling behavior and the small-signal settling behavior of S/H. The relationship among settling time, feedback factor, poles of the OPA, bias current, signal swing, and setting accuracy is deduced. For a setting time of 3ns, the bias current of OPA is deduced regarding the former relationship. The gain-boosted folded-cascode architecture has been chosen for the OPA. The gain and the GBW, as well as the phase margin of the OPA are designed to achieve minimum setting time. 4) Based on SMIC 1.8V 0.18μm mixed-signal CMOS process, a 12bit 100MSample/s S/H circuit is designed with Hspice simulation environment and Virtuso layout tool.