多频段射频CMOS功率放大器的研究与设计

【作者】 李林真；

【导师】 李竞春；

【作者基本信息】 电子科技大学 ， 微电子学与固体电子学， 2009， 硕士

【摘要】 射频功率放大器模块是无线通信收发器中的重要模块,主要应用于各种无线发射机中,它的作用是放大高频信号至所需的功率,并送至天线辐射出去。功率放大器作为射频收发机中功耗和体积最大的模块,其性能直接决定了整个射频收发机的体积、功耗和成本,因此研究射频CMOS功率放大器对实现单片射频收发机意义重大。随着第三代移动通信标准的提出和应用,各种无线通信标准的发展对射频集成电路提出了多模式、多频段的新要求,也因此对收发机的射频部分提出了新的要求—具有多频段多模式工作的性能。本文通过深入分析射频CMOS功率放大器的系统结构和工作原理,并针对目前移动通信主流标准(GSM0.9GHz/PCS1.9GHz),设计了一个并行式多频段功率放大器。首先本文对功率放大器的基本特点、主要性能指标,器件非线性的影响以及RLC网络进行了分析,对线性和非线性功率放大器进行了系统总结,然后研究了在CMOS工艺下,射频功率放大器的局限性,并用于指导功率放大器设计。其次,本文详细研究了本文所关注的并行式多频段功率放大器的工作原理,对多频段输入输出阻抗匹配进行了深入的理论分析及其优化;针对CMOS工艺晶体管击穿电压低和跨导能力有限等缺点,本文在电路设计中采用单端三级拓扑结构;并且在偏置电路的设计中,实现了一个高精度,高电源抑制,电路实现简单,可用于低压的电流基准。设计的射频多频段A类功率放大器能同时满足输出功率,增益,效率和线性度的要求。最后,基于TSMC 0.35μm RFCMOS工艺,采用Cadence的SpectreRF进行电路仿真。仿真结果表明,在使用片上电感后,在两个频段上1dB压缩点均大于22dBm,输出功率达到23dBm,功率增益为23dB,功率附加效率达到30%。更多还原

【Abstract】 Power amplifier (PA) is the key block of the wireless communication transmitter in RF, whose function mainly determines the cost, the power and the size of the transceiver. In order to meet the requirements of low cost, low power and small size, RF transceiver needs a CMOS power amplifier.With the development and application of the third wireless communication standards, multi-band and multi-mode application requirements are brought to RF IC design as well as the power amplifier of transceiver. Through the analysis of systematic structure and the basic theory of power amplifier, a concurrent multi-band power amplifier is presented according to the mobile communication standards, GSM0.9GHz and PCS1.9GHz.Firstly, the basic charecteristic of power amplifier, non-linear effects of devices and RLC network are introduced and discussed. Then the limitations of the CMOS process for power amplifiers are proposed,and they will be used as the instructions of the design of power amplifer.Secondly, the theory of concurrent power amplifier is studied and discussed in details as well as analysis and optimation of multi-band input and output match. Owing to the low breakdown voltage and limited transconductonce amplification ability of the CMOS process, the design of the single-ended three-stage topology is proposed. Besides in the application of bias circuits, a reference of high pricision and high power supply rejection (PSR) is presented which can also be used in low voltage supply application.Finally, based on TSMC 0.35μm RFCMOS process, the multi-band power amplifer is simulated by Cadecce tool. The simulation results show that, the 1dB compression point is above 22dBm, the output power is 23dBm, the power gain is 23dB, and the peak power added efficiency (PAE) is 30%.更多还原