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适宜于高精度流水线ADC的校正算法研究
【作者】 王妍；
【导师】 于奇；
【作者基本信息】 电子科技大学 ， 微电子学与固体电子学， 2009， 硕士
【摘要】 流水线模数转换器(Pipeline Analog-to-Digital Converter, ADC)因拥有高速、高精度、低功耗和芯片占用面积小的优势而被广泛应用于宽带通讯系统以及视频图像处理。但运放有限的开环增益和电容失配等非理想因素降低和限制了它的线性度。校正技术是充分利用现有的集成电路设计和制造技术水平,降低误差对ADC性能影响、提高ADC精度和动态范围的有效手段,是ADC的重要研究方向之一。本文对用于流水线模数转换器的增益误差后台校正技术和电容失配后台校正技术作了深入研究。论文提出了一种用于multi-bit流水级的数字后台增益误差校正方法。该方法应用改进冗余位结构,通过在其子DAC输出端引入伪随机信号测量级间增益,并利用此估计值在后台进行增益误差补偿。利用Matlab对12位流水线ADC进行系统模拟,当首级有效精度是3位且相对增益误差为±2%时,经校正后,INL均为0.16 LSB,DNL分别是0.13 LSB和0.14 LSB,SFDR与SNDR各自提高了35 dB与16 dB。基于0.18um SMIC Si-CMOS模型,采用HSPICE对校正系统中关键电路进行了设计和模拟,仿真结果与Matlab模拟结果完全吻合。分析表明,该增益误差校正方法能有效补偿multi-bit级增益偏大或偏小的误差,进而实现增益误差校正,且不会降低ADC转换范围与增加额外的比较器。论文采用一种基于伪随机信号的数字后台校正方法对1.5-bit流水级中的电容失配误差进行校正。该方法改变传统的1.5-bit冗余位结构,在其子DAC输出端引入伪随机信号,使传输曲线根据伪随机信号和输入信号范围发生抖动,再将得到的残差电压与相同的伪随机信号在后台作相关运算,并求其均值得到校正参数,然后利用测量到的值对电容失配误差进行补偿。利用Matlab对12位流水线ADC进行系统模拟,当首级电容失配因子为±0.25%,输入电压为0.999满幅度时,经校正后,SFDR分别提高了16 dB和19 dB。基于0.18um SMIC Si-CMOS模型,采用HSPICE对校正系统中的关键电路进行了设计和模拟,仿真结果与Matlab模拟结果完全吻合。分析表明,该电容失配校正方法是有效的,同时,它能在不牺牲ADC转换范围的条件下允许大幅度伪随机信号的引入,从而可以提高校正速度。
【Abstract】 Pipeline ADC (Analog-to-Digital Converter) is widely used in wide-band communication systems and video imaging, due to its advantages of high speed, high resolution, low power consumptions and low die areas. However, its linearity is limited by opa’s finite open-loop gain, capacitor mismatch, and other non-ideal factors. Calibration is one of the important research fields of ADC, since it can effectively reduce effects of errors and improve ADC’s resolution and dynamic range, under the modern IC design and manufacture level.Backend calibrations on gain errors and capacitor mismatch in pipeline ADC are studied in this paper. A digital backend gain calibration method for multi-bit stages is proposed. Using a reformative redundant stage, gain errors are measured by PR (pseudo-random) signal being injected at sub-DAC output and compensated in background according to the estimated value. Simulations are performed for a 12-bit pipeline ADC. Assumed the relative gain error of 3-bit first stage is±2% respectively, with calibration simulations show an improvement of 35 dB in SFDR, 16 dB in SNDR,0.16 LSB of INL under both conditions, 0.13 LSB and 0.14 LSB of DNL respectively. Based on SMIC 0.18μm Si-CMOS process model, the key calibration circuits are designed and simulated using HSPICE, and the results are the same to that of Matlab. Analyses show that the proposed method can calibrate positive or negative gain errors in multi-bit stage without reducing the conversion range or increasing extra comparators.A digital backend calibration method based on PR signal is used to calibrate capacitor mismatch in 1.5-bit pipeline stage. Using modified 1.5-bit redundant stage, injecting PR signal at sub-DAC output to get residue voltages, while the transfer curves dithering with PR signal and input signal range, then correlating residue voltages with the same PR sequence to obtain calibrated coefficients, which are used to compensate the mismatch errors. Simulations are performed for a 12-bit pipeline ADC with 99.9% full-scale sine-wave. Assumed the error of first stage is±0.25% respectively, with calibration simulations show an improvement of 16 dB and 19 dB in SFDR respectively. Based on SMIC 0.18μm Si-CMOS process model, the key calibration circuits are designed and simulated using HSPICE, and the results are the same to that of Matlab. Analyses show that this backend calibration for capacitor mismatch is effective; in addition, it can shorten the calibration time by allowing the injection of a large dither without sacrificing the signal range.