【作者】 刘海广；

【导师】 王春华；

【作者基本信息】 湖南大学 ， 信息与通信工程， 2009， 硕士

【摘要】 本文主要研究了差分式电流控制电流传输器的原理及设计方法。首先介绍了电流模式电路的发展现状及其特点,并与传统电压模式电路做了简单的比较;然后介绍了电流模式电路的基本模块-电流传输器的发展历程、原理及性能。在阅读了大量电流模式电路及电流传输器文献的基础上,结合国家自然科学基金项目(新型差分式电流传输器及其构成的电流模式连续时间滤波器NO.60676021),首次提出了全差分式电流控制电流传输器(FDCCCII)和全平衡差分式电流控制电流传输器(CFBCCII)两种新型电路;然后分别以提出的FDCCCII和CFBCCII电路为基本单元,设计了两种新型滤波器;最后对提出的CFBCCII电路和由其构成的滤波器利用Cadence进行了版图设计,采用Hspice进行了前仿真、后仿真,并参加了上海集成电路设计中心(ICC)的多项目晶圆计划(MPW)采用Chartered 0.35μm工艺去新加坡进行了流片实验。本文的主要创新工作如下:(1)提出了一种新型全差分式电流控制电流传输器(FDCCCII)。提出的电路采用差分式输入、输出电路结构,具有较强的共模信号和偶次谐波抑制能力;引入了双极性BJT跨导线性环,因而该电路端口电阻具有可控性;提出的电路既具有BJT速度快的特点又具备了CMOS功耗低的优势,可用BiCMOS工艺实现;最后利用Pspice采用0.5μm工艺进行了仿真,验证了提出的电路的可靠性。(2)提出了一种新型全平衡差分式电流控制电流传输器(CFBCCII)。提出的电路采用全平衡差分式输入输出,电路结构严格对称,同时引入了共模反馈电路,因此,具有极强的共模信号和偶次谐波抑制能力;该电路采用并行MOS跨导结构电压传送电路,从而具有端口可控性,并且消除了传统CCCII电路中MOS管尺寸严格匹配而工艺上难实现的缺陷;提出的电路全部由MOS管构成,电路功耗很低,可用CMOS工艺轻松实现集成,最后利用Hspice采用Chartered 0.35μm工艺完成了仿真,并参加ICC的MPW计划进行了流片实验。(3)分别基于提出的电路提出了两种新型有源滤波器。基于FDCCCII电路设计了一个差分式滤波器,其Q、?均可独立可调,并利用Pspice采用0.5μm工艺进行了仿真验证;基于CFBCCII电路提出了一个仅有一个CFBCCII模块及两个接地电容构成的滤波器,?独立可调,结构简单,易于集成,利用Hspice进行了仿真验证,最后采用Chartered 0.35μm工艺成功地进行了流片实验。更多还原

【Abstract】 The thesis mainly studies the principle, design and methods of differential current controlled current conveyors. Firstly, it introduces the development and character of the current-mode circuit, and compares current-mode circuit with voltage-mode circuit simply. Afterwards, the development and character of the basic models of current mode circuits-current conveyors are introduced. Then, a new fully differential current controlled current conveyor(FDCCCII) and a new current controlled fully balanced current conveyor(CFBCCII) are firstly proposed after reading a lot of papers about current conveyors and combining with the project supported by National Natural Science Foundation of China (No. 60676021). Then, two new current mode active filters are brought forward on the base of the proposed circuit models. At last, the CFBCCII and the relative filter circuits are simulated by Hspice in order to verify the reliability, then the layouts of all the circuits are designed with Cadence. At last, the chips are taped out successfully in Singapore with the plan of MPW offered by ICC. The main contents are as follows:(1) A new fully differential current controlled current conveyor is presented in this paper. The proposed circuit is well capable of eliminating the common mode (CM) signals because of the differential input and output configurations, and the port parasitic resistor is controllable with using the bipolar junction transistor (BJT) translinear loop configuration. The proposed circuit owns the advantages of high speed and low power energy because of the characters of the BJT and MOS devices, which is able to be realized by BiCMOS technology. At last, the circuit is simulated by Pspice with 0.5μm technology in order to verify the reliability.(2) A new current controlled fully balanced current conveyor is presented in this paper. The proposed circuit can eliminate the common mode (CM) signals very strongly with the differential input, strictly symmetrical and CMFB circuit configurations. The port resistor is controllable because of the using of the parallel MOS transistor configuration.Moreover,the circuit eliminates the rigor MOS size condition of traditional CCCII circuit, therefore it is easy to be realized .Othermore, it’s also easy to be integrated for that there are only MOS devices in this circuit. At last, the circuit is simulated by Hspice in order to verify the reliability of the circuit, and the chip is taped out successfully with the Chartered 0.35μm technology with the plan of MPW offered by ICC.(3) Two new active filters are presented on the base of the above proposed circuits. A new differential active filter with the controllable Q and ? is presented based on the FDCCCII circuit,and the filter circuit is simulated by Pspice in order to verify the reliability of the circuit; Another new active filter composed of only one CFBCCII and two grounded capacitors with the controllable ? is also presented based on the CFBCCII circuit, which is easy to integrate because of the simple circuit configuration, and the circuit is simulated by Hspice in order to verify the reliability of the circuit.At last, the circuit is taped out successfully with Chartered 0.35μm technology.更多还原