【作者】 刘仁品；

【导师】 聂红儿；

【作者基本信息】 北京工业大学 ， 通信与信息系统， 2009， 硕士

【摘要】 全球移动通信正在飞速发展,各种新的移动数据业务也在不断地出现。手机电视业务的出现,将带给人们全新的收视体验,让人们无论在机场,公园,商场还是出租车上都能实时地收看电视节目。中国移动多媒体广播(China Mobile Multimedia Broadcasting,CMMB)作为中国自主研发的手机电视标准,代表着中国自主的知识产权,拥有巨大的市场前景。CMMB信号采用无线传输,为了保证传输的可靠性,就需要对信息进行纠错编码。RS(Reed-Solomon)编码作为一种重要的信道编码,有着很强的纠错能力,配合上字节交织,尤其对突发错误的纠正效果相当不错。CMMB系统中规定用低密度奇偶检验(Low Density Parity Check,LDPC)编码配合RS编码作为前向纠错(Forward Error Correction,FEC)的组成部分。本文主要针对FEC中RS解码器的设计进行研究。CMMB接收机由于装在移动设备上用于接收移动数据,而其数据量并不是很大,因此对RS解码器的速度要求并不高,而由于移动设备基本都靠电池供电,因此低功耗就成为本文设计的一个主要要求,因此本文中的设计主要以降低RS解码器的面积和功耗为目的,而以牺牲RS解码器的速度为代价。本文中介绍了几种常用的RS译码算法,通过比较最后确定以修正欧几里德算法为设计的基础。在硬件设计上,参考了各种相关论文中RS解码器的设计,对解码器的各子模块进行了分析,分别选取了一种面积和功耗都比较合适的设计,其中伴随式计算电路部分通过对算法的分析进行了独创的改进,减小了一定的功耗,而面积几乎没有增加。修正欧几里德算法部分通过对系统需求的分析,选择了一种速度较慢但是面积和功耗都比较低的设计。错误位置和错误值的部分本文参考经典设计进行了复用。另外,在整体结构上,本设计结合CMMB接收系统的特点,去掉了用作延时单元的存储器,减少了对硬件资源的占用。最后,用Verilog语言实现了本文中涉及到的各种设计,通过对各实现分别进行综合和仿真,将各种设计的面积和功耗进行了比较分析,验证了本设计可以在CMMB系统中使用,并证实了本文中各种降低功耗和面积的改进是有效的。更多还原

【Abstract】 Wireless communication is developing rapidly and many new services appeared. Mobile TV as a new service will bring a new experience to us. We can watch TV either at an airport, a park, a department or in taxi in the future. CMMB is a standard of mobile TV developed by China. It stands for the intellectual property of China and will be used widely.CMMB signal is transmitted wirelessly. For receive the correct information, forward error correction is necessary. RS coding is an important channel coding technology. It has a good performance at error correction. Concatenated with byte interleaving, it works well especially for burst error. RS and LDPC coding is used as part of FEC in CMMB system.In this thesis, we focused on the design of RS decoder. CMMB receiver is equipped on mobile device. The data rate is not very high, so decoding speed is not very important for our decoder. Low power consumption is necessary because mobile device always powered by a battery. The design described in this thesis is focused on low power and low area, while this design may slow down the decoding speed.We introduced some RS decoding algorithm and compare them. Finally we choose the MEA algorithm as the base of our design. After referenced some papers on RS decoder, we designed each sub modules of RS decoder. According to analysis of algorithm, syndrome computation circuit is modified for decreasing power consumption, and the area is almost not increased. MEA circuit is designed for low power while slowing down the decoding speed. The last part is the error location and error value computation circuit and typical design is used for this part. Considering the structure of CMMB receiver, delay cell is not used in this design. This brings us low area and low power. At last, we implemented designs mentioned in this thesis on Verilog language. Synthesis and simulation is done for these designs and the result proves that the design in this thesis is available.更多还原