【作者】 章建钦；

【导师】 李开航； 陈松岩；

【作者基本信息】 厦门大学 ， 微电子与固体电子学， 2008， 硕士

【摘要】 近十几年来,随着微电子技术的快速发展和计算机技术在集成电路中的应用,集成电路已发展到超大规模甚至是单片系统集成阶段,大大促进了数字技术的发展。数字技术具有速度快、精度高、抗干扰能力强等优点而得到广泛的应用,越来越多的电子设备已经从采用模拟电路实现而大范围地向数字化转变。随着数字化进程的深入,作为连接模拟和数字世界桥梁的模数转换器也同样成为研究热点,其中高位的∑-△型A/D转换器作为高精度信号处理中的重要接口部件,由于其转换精度高而使它们在当今高精度信号处理领域中倍受青睐。因此本论文以实现性能良好的高位∑-△型A/D转换器芯片为目标,设计和实现一款24位∑-△型A/D转换器的关键部分——数字抽取滤波器。本文先简要介绍∑-△A/D转换器在高精度信号处理中的应用和数字抽取滤波器在∑-△A/D转换器中的作用,接着对∑-△A/D转换器的基本工作原理进行了介绍,其中着重分析了过采样技术和噪声整形技术的基本原理,然后对数字抽取滤波器的原理和实现结构进行了研究,特别介绍了抽取的原理、抽取滤波器的多级结构以及多级结构中的前级梳状滤波器和后级半带滤波器的等方面的原理。本论文设计的数字抽取滤波器采样频率为256KHz,输出数据率为20Hz,要求整个滤波器实现12800倍降采样,其中级联积分梳状滤波器实现3200倍降采样,半带滤波器实现最后的四倍频降采样。积分梳状滤波器采用无乘法器、结构规则、易于版图实现的递归结构来实现,而半带滤波器则采用运算量低、节省硬件资源的转置型结构来实现。设计首先使用MATLAB对滤波器整体进行仿真,由设计指标定出了各部分结构的参数,然后采用CSMC 0.5um工艺规则完成滤波器的整体版图设计,最终完成了流片和测试。测试结果表明,所设计的数字抽取滤波器实现了抽取滤波的功能,且整体性能良好,达到预期目标。更多还原

【Abstract】 With the rapid development of microelectronic technology and the aid of computer technology in IC design and development, the scale and complexity of integrated circuits have been increasing exponentially over the past few decades. Due to its flexibility, high resolution, strong anti-interference and fast increasing processing power, more and more applications are using digital circuits and digital technology. Powerful digital circuits and digital processing technology demand higher performance analog-to-digital converters (ADC), which is the interface between analog and digital worlds. This encouraged research activities on high performance ADCs. Among these high performance ADCs, sigma-delta ADC technology has been proven to be an excellent technology choice for implementing high resolution ADC in large-scale digital CMOS process. Its popularity has made it a critical component in many applications.In this thesis, a brief introduction is given to the application of sigma-delta A/D converters in high-resolution signal processing applications, and the role of decimation filters in sigma-delta A/D converters. The second part explains the basic theory of sigma-delta A/D converters; include the analysis of oversampling and noise shaping technology, followed by a summary of research results in the theory and implementation of digital decimation filters, including comb filters and half-band filter as decimation filters.The sampling frequency of the designed digital decimation filter is 256kHz. The output data rate is 20Hz. The filter’s decimation ratio is 12800, with decimation ratio of 3200 realized by the CIC filter and decimation ratio of 4 realized by the half band filter. The CIC filter is implemented using a recursive structure. The half band filter is realized with a transpose structure. Matlab computer software is used in the design and simulations of the filter. The filter is fabricated in CSMC 0.5um CMOS process. The test results verified the filter’s functionality. The design goals and targets have been successfully achieved.更多还原