【作者】 朱振华；

【导师】 乐孜纯；

【作者基本信息】 浙江工业大学 ， 通信与信息系统， 2009， 硕士

【摘要】 随着WDM技术的广泛应用,传送网的带宽问题得到了解决。由于IP网络规模的不断扩大,需要一种新的光交换方式来解决目前传送网节点交换能力不足的问题。光突发交换结合光分组交换和光路交换的优缺点,在交换性能和可实现技术上做了折中,因此成为了近期解决传送网节点交换能力问题的一个研究热点。光突发交换最大特点是采用单向预留资源的方式而不需使用光缓存器,边缘节点中的控制模块正是在整个网络实现这种预留机制的一部分。在本文中首先设计了基于JIT和JET两种资源预留机制的控制模块,以实现结构相对复杂的JIT协议为侧重点。在设计中为了提高模块的吞吐量采用在不同层次上使用并行结构的思路,提出Time Process Machine模块来处理协议中产生的各种时间事件,设计了总线控制模块来解决多对模块之间的请求冲突,并对BDP、BCP收发模块以及设计中的相关参数做了详细说明。本文采用FPGA可编程芯片完成对设计的硬件实现,并使用QuartusⅡ软件进行辅助设计,最后得出两类模块的理论最高时钟频率为118.84MHz和123.73MHz。在使用软件时序仿真和示波器实测芯片输出波形后所得到的结果表明:设计的控制模块能够实现JIT和JET控制协议预留资源的功能以及BCP、BDP的收发工作,特别在模块内处理产生的时延对偏置时间的影响非常小。更多还原

【Abstract】 With the comprehensive application of the WDM technology, the bandwidth problem of the transport network has been solved. Because of the explosive growth trend of Internet traffic, demanding a new optical switch to solve the lack of the switch ability in the node of transport network. Optical burst switch (OBS) is a compromising method giving attention to the advantages of both optical packet switch and optical circuit switch, therefore the OBS becomes one of the key issues in optical networks.The most important characteristic of OBS is adopting one-way resource reservation mechanism, and the control module in the edge node is one of the parts to implement the mechanism in the whole network. Two hardware design schemes which based the Just in time and Just enough time resource reservation protocols are reported in this paper, emphasizing the JIT protocol which is more complexity to the JET protocol in the edge node comparatively. A parallel structure based on the different hierarchies is adopted for the sake of increasing the throughput, Time Process Machine is proposed to deal with the time event, bus control module is designed to solve the request conflict between several modules, sending and receiving module of burst control packet and burst data packet are also interpreted detailedly.The design scheme bases on the FPGA chip and is compiled successfully in the Quartus II software. Timing analyse results show that the working clock in theory of the two types of the control module can get as much as 118.84 MHz and 123.73 MHz respectively. Through timing simulation and waveforms form oscillograph, it is indicated that the schemes can accomplish the function of the control module preferably, specially the disposal delay caused by module would not affect the actual offset time badly.更多还原