【作者】 刘昕琦；

【导师】 叶明；

【作者基本信息】 南京航空航天大学 ， 通信与信息系统， 2007， 硕士

【摘要】 LDPC码(低密度奇偶校验码)是一种具有极强纠错能力的差错控制编码技术,它的性能接近香农极限,其译码复杂度低于Turbo码,由于LDPC码在光通信、卫星通信、深空通信、第4代移动通信系统、高速与甚高速率数字用户线、光和磁记录系统等诸多领域都有良好的应用前景,所以,开发LDPC硬件译码器已经成为纠错编码领域研发的一大热点。本文首先概述了LDPC码的定义、基本构造方式和编码理论;讨论了LDPC译码方法——BP译码算法,为方便译码器的硬件实现本文着重研究了低实现复杂度的Log-BP译码算法,通过对两种算法进行了性能仿真,结果表明Log-BP在性能上完全适合,可以作为硬件译码的算法。在硬件实现中,考虑到译码精度要求和硬件资源有限,本文探讨了数据量化位数选择与译码性能的关系并进行了仿真,得出了在本译码器设计指标和现有硬件资源条件下,最合适的量化数据位数。在此基础上,使用Verilog硬件描述语言,采用部分并行译码结构,利用自顶而下的模块化设计方法设计LDPC译码器,并运用EDA设计工具ModelSim和ISE,对各个组成模块进行综合和时序仿真;然后利用原理图输入法将分模块合并为一个完整的译码器电路,对整个译码器进行了全面的功能仿真、综合和时序仿真,验证设计的正确性和译码器的性能。最后,设计了译码器实验板,下载了译码算法,进行了相应的测试。更多还原

【Abstract】 LDPC code(Low Density Parity Check Code)is a powerful error correcting technique.Mackay and Neal prove that the performance of LDPC codes is close to the Shannon limits .Its decoding complexity is also lower than turbo code. Recently, LDPC code has drawn the worldwide attentions successfully because of its excellent performace and its bright application prospect in optic communications, satellite communications, deep space communication,the fourth generation mobile communication system ,digital subscriber loop with high speed or hypervelocity, optical and magnetic recording system, many companies are urgent to develop LDPC decoder on hardware.This paper firstly introduces the definition of LDPC codes, the basic construction of LDPC codes and the way of encoding,they are the foundations of decoding Secondly, we discuss the Belief Propagation (BP) algorithm and the Log-BP algorithm and simulate the Log-BP algorithm.The Log-BP algorithm is suitable for the implementation of the hardware decoder.Thirdly, given the decoding precision and the limit hardware resources,we discuss the selection of digital bit, and we offer the most suitable option. Fourthly,this thesis uses Verilog Hardware Description Language and adopts part parallel decoding configuration. We use the idea of top-down design to program the decoder with Verilog Hardware Description Language. Moreover, we synthesize and analyze the static time of the design with ModelSim and ISE to verify the correctness and the function.At last, we use the FPGA and relative hardware cells to design a decding board.更多还原