【作者】 郑思喆；

【导师】 王德君；

【作者基本信息】 大连理工大学 ， 电路与系统， 2008， 硕士

【摘要】 随着计算机技术、多媒体技术、信号处理技术、微电子技术的迅速发展,先进的电子系统不断涌现,在现代先进的电子系统前端和后端都将应用数模转换器,而且需要更高的速度和分辨率。所以本文设计了一个12位100MSPS分段式电流舵型高速数模转换器。本文介绍了数模转换器的基本结构和基本原理,介绍了当今数模转换的状况和发展动态,分析了电流、电压和电荷三种类型的数模转换器,对数模转换器静态参数和动态参数进行了具体的分析。通过对二进制码和温度计码结构的分析,综合考虑数模转换器的性能参数,选择了一种6+6,低6位二进制码高6位温度计码结构的电流舵型数模转换器。本文进行了详细的理论和实际问题的分析与解决,并给出了寄存器电路,温度译码电路,选通电路,锁存电路,时钟电路,基准源电路,电压电流转换电路,单位电流源阵列电路和开关阵列电路的设计方案和具体电路。通过对数模转换器各个模块的原理分析与结构设计,并对整体电路进行仿真,调试,版图绘制,完成了完整的数模转换器设计。采用了本文设计的电路结构,得到了100MHZ采样频率,输入频率50MHZ,转换速度为2.82ns的12位数模转换器。而且微分线性误差小于0.6LSB,积分线性误差小于1.8LSB,SFDR 71.0dB,THD -82.0dB,SNR 70.1dB,SNDR 70.1dB,电路的最大功耗为188.1mW,电路的总体版图面积为3.78mm~2。更多还原

【Abstract】 With the development of the computer, the multimedia, the signal processing and the microelectronic, the advanced electronic system comes forth continuously. The Digital-Analog Converter will be used in the front end and back end of the advanced electronic system and it needs the higher speed and resolution. This paper designs a 12b 100MSPS sectional coding current steering DAC.This paper present a general introduction on D/A converter of basic structure and principle, study of domestic and aboard, the analysis of different converting type such as current converting, voltage converting and charge converting, and the analysis of static parameter and dynamic parameter of D/A converter. Based on the study of binary code D/A converter and thermometer code D/A converter, and the performance parameter of D/A converter, a 6+6, low 6b to be binary code and high 6b to be thermometer code, current steering D/A converter has been designed. Some of the basic design theory and technology are presented within this paper. To improve this D/A converter, some of the cell architectures, including register, thermometer decoding, gate circuit, latch, clock, reference voltage and current, current source array, switch array, have to be designded carefully. The details of these cells are described in this paper. Through the analysis of principle and the design of structure of each module, and the simulating, debugging and drawing of layout of D/A converter, it has completed the whole design of the D/A converter.This architecture implements the 12 bit D/A converter and achieve a speed of 100MSPS, 50M input frequency, switching speed 2.82ns, DNL less than 0.6LSB, INL less than 1.8LSB. SFDR 71.0dB, THD -82.0dB, SNR 70.1dB, SNDR 70.1dB, the maximum power dissipation 188.1mW, and area is less than 3.78mm~2.更多还原