【作者】 石美美；

【导师】 殷福亮； 陈喆；

【作者基本信息】 大连理工大学 ， 电路与系统， 2009， 硕士

【摘要】 回波抵消器作为消除通信系统中电学回波和声学回波的功能单元,在免提电话、无线产品、IP电话和电话会议等系统中有着非常重要的应用。传统回波抵消器主要是基于通用DSP处理器实现的。这种回波抵消器在系统实时性要求不高的场合能很好的满足回波抵消性能要求,但是在实时性要求较高的场合,其处理速度等性能方面已经不能满足系统需求。现代大容量、高速度的FPGA的出现,克服了上述方案的诸多不足。基于FPGA来实现数字信号处理可以很好地解决并行性和速度问题,且其灵活的可配置特性使得FPGA构成的DSP系统易于修改、测试和硬件升级。本文主要针对电话系统中的电回波进行研究,设计自适应回波消除器并基于FPGA平台进行实现。在整个回波抵消系统的实现过程中,本文主要做了如下几方面工作:首先,研究并完成了回波消除器的各个功能模块。各功能模块算法中,重点分析了LMS、NLMS、DLMS等运算量较小而收敛速度和稳态残留回波又能满足要求的几类自适应算法。其次,本文介绍了Altera公司的StratixEP1S25DSP开发板以及所使用的硬件描述语言Verilog HDL。结合QuartusⅡ集成开发环境,描述了基于FPGA的设计流程和实现方法。然后,本文在给出总体设计方案后,利用硬件描述语言Verilog HDL在FPGA硬件平台上实现了各模块算法。在QuartusⅡ集成开发环境下对回波抵消系统进行模块级和系统级的功能仿真、时序仿真和验证后,给出了各功能模块的仿真结果和实现性能。最后,根据ITU-T G.168协议所规定的要求,对所设计的回波抵消器进行了各项性能测试。更多还原

【Abstract】 Echo canceller, a working cell that cancels electrics echo or acoustics echo in communication systems, has important application in systems such as hand-free telephone, wireless product, IP telephone, audio conference and so on.Traditional echo canceller is usually implemented on general DSP processor. Such echo canceller can satisfy requirement of echo cancellation performance on this condition that has lower request of real-time quality. But when the request of real-time is high, the performance such as processing speed can’t meet the requirement of real-time processing. FPGA which is bulky and high-performance makes up for the deficiencies as mentioned above. Implementing digital signal processing based on FPGA can resolve problems of both parallel and speed. The characteristic of flexible reconfiguration makes that DSP system easier to implement, test and upgrade.This thesis is focused on electrics echo canceller in PSTN. An applied adaptive echo canceller based on FPGA platform is designed and implemented. During the process of implementing the whole echo canceller system, The following research works are carried out.Firstly, all models of the echo canceller are thoroughly researched and completed using C language. Integrated with application, we put more emphasis on the adaptive filtering algorithms including LMS, NLMS, DLMS, which can get a tradeoff between the convergence performance and the computational complexity.Secondly, the Altera StratixEP1S25DSP development board and Verilog Hardware Description Language are introduced. Combined with the integrated developing environment Quartus II, the flow of FPGA design is also described.Finally, after the total design scheme is given, all models are implemented on FPGA platform using Verilog Hardware Description Language. The whole echo cancellation system is functional and timing simulated in Quartus II environment. Simulation results and relevant performance are given too.更多还原