【作者】 吴志伟；

【导师】 邹雪城；

【作者基本信息】 华中科技大学 ， 微电子学与固体电子学， 2007， 硕士

【摘要】 近几年来,移动电话、个人数字助理和数码相机等消费类电子产品需求的不断增长推动了液晶显示器市场的发展,从而也为控制器带来了广阔的市场前景。由于功能的不断增加,液晶显示控制器正变得越来越复杂,对其验证的难度也呈指数级增长。本文主要讨论当前各种流行的验证方法,并详细叙述了如何对一个液晶显示控制芯片进行尽可能完备的系统验证。寄存器传输级代码的验证是保证芯片功能正确的最关键因素,为此,本文讨论了逻辑功能仿真验证和原型验证这两种方法。在逻辑功能仿真验证方法中,首先通过代码静态检查保证代码风格。在详细研究设计规格说明书的基础上,构建了一个可重用的验证平台,综合运用了总线功能模型和可编程语言接口等方法。最后,对验证平台的覆盖率进行了详尽的分析以保证仿真的完备性。对于原型验证,使用FPGA作为目标器件来构造原型,模拟可能的流片结果,在实际应用环境中进行测试。现代ASIC设计需要经历众多流程,每一道流程都必须保证设计的正确性和相关的性能指标。正是基于这一点,本文还讨论了如何在设计流程中对网表和版图等设计形式进行验证。针对门级网表,主要进行功能和时序的收敛性验证,包括形式验证、静态时序分析和动态后仿真等。针对物理版图,主要进行版图的可靠性验证,确保所实现出来的设计对象没有物理违规,包括设计规则检查和版图原理图一致性验证等。此外,芯片制造工艺的不断复杂化导致了成品率的降低,为了验证制造过程的正确性,对流片回来的硅片进行验证是必不可少的流程。本文针对液晶显示控制芯片,介绍了两种硅验证手段:扫描测试技术和存储器内建自测试技术。更多还原

【Abstract】 At present, the demand of consumer electronics product has been growing a lot, such as mobile phone, personal digital assistant and digital camera. This trend not only increases the Liquid Crystal Display market, but also brings a bright prospect for LCD Controller. Due to the continuing increase of function, LCD Controller has becoming more and more complicated, so the difficulty of verification also presents an index rise.All popular verification method is mainly discussed in this thesis, and a full system verification methodology based on LCD Controller monolithic is proposed here. Register transfer level code verification is the most important factor in the design, therefore, two ways are analyzed in this thesis: logic function simulation and prototype verification. In the first way, code static check could be used to guarantee the coding style. After the detailed research of design specification, a reused verification platform was constructed using bus function model, programmable language interface, etc. The analysis of coverage is necessary for the platform. FPGA is used in the second way for emulation, to assure the chip function under real circumstance.Many design flows are required in the modern ASIC design, every flow can bring mistake and performance degradation, so how to verification netlist and layout in the design flow is also discussed in this thesis. For gate netlist, formal verification, static timing analysis and dynamic post-simulation are used to assure function correctness and timing closure. For physical layout, the main means are design rule check and layout vs schematic. The more and more complexity of chip manufacture lead to the reduction of finished semiconductor device rate, so chip test is necessary before sale. For the LCD Controller, two silicon verification ways are proposed: scan test and memory built-in self-test.更多还原