【作者】 贺磊；

【导师】 于宗光；

【作者基本信息】 江南大学 ， 微电子学与固体电子学， 2008， 硕士

【摘要】 随着集成电路设计工艺水平的不断提高,高性能、低成本已成为SOC芯片设计的主要挑战,作为片上时钟发生器锁相环的设计变得非常关键。电荷泵锁相环具有易于集成、低功耗、低抖动、频率牵引范围大和静态相位误差小等优点,成为了当前数字锁相环产品的主流。本文设计了一款面向16位定点DSP芯片的三阶电荷泵锁相环。文章在深入分析电荷泵锁相环设计理论的基础上,根据DSP芯片对锁相环的具体应用要求,确定了锁相环的总体电路结构和各项性能参数。然后将各项参数指标分到各个模块上,进行单元电路的设计。在单元电路的设计时,论文重点讨论并解决了下述问题:1)鉴频鉴相器的优化设计,在降低死区的同时,有效地增加鉴相带宽;2)采用开关在源极的新型电荷泵结构,在消除电荷共享效应的同时,具有开关加速的功能以及很高的电流匹配精度;3)使用二阶无源RC环路滤波器降低了输出纹波,并对滤波器参数进行了优化设计;4)压控振荡器采用四级延迟单元的环形振荡器,每级采用RS触发结构来产生差分输出信号,在有效降低静态功耗的同时,具有较好的抗噪声能力;5)采用全定制设计的可编程分频器,在尽可能的减少设计单元的同时,实现对输出不同频率的调节要求。所设计的电荷泵锁相环采用SMIC 0.35μm CMOS工艺实现,5V电源供电,其面积为502μm×496μm。仿真结果表明,锁相环的频率捕获范围为2MHz～60MHz,在VCO输出频率为20MHz时,环路的锁定时间为12.7μs,抖动的峰峰值小于512ps,功耗为6.2mW,能完全满足DSP芯片时钟系统的要求。最后,为了DSP系统仿真的需要,论文还对所设计的电荷泵锁相环建立了Verilog功能模型,并对今后下一步工作中建立锁相环IP核,实现锁相环的可复用性作了展望。更多还原

【Abstract】 With the rapid development of IC design and process, high performance and low cost are now the main challenges for SOC design. Phase-locked loop(PLL) used as clock generator on chip becomes very critical. Because of the merit of integrated easily, low power, low jitter, small phase difference error and big capture scale, the CPPLL(Charge-pump PLL) has become one of the major digital PLL product.This paper presents a third-order CPPLL used in the 16-bit fixed-point DSP. Based on the analysis of the theory of CPPLL and application requirements in the DSP, the structure and the performance specifications of the PLL are defined, and then the subcircuits are designed. During these procedures, this thesis discusses and solves the following problems:1) Optimizes the PFD(Phase and Frequency Detector) to reduce the Dead-zone and increase the bandwidth of phase detector;2) Adopts a new type of CP(Charge-Pump) with accelerated switch in source, it solve the effect of charge sharing and with high current matching accuracy;3) Adopts a second-order RC filter to reduce the output ripple, and optimizes the parameters of the filter;4) Adopts a ring VCO which consists of four stage of delay elements, each of them adopts the RS flip-flop to generate difference output. This structure reduces the power dissipation effectively and with much better performance in anti-noise;5) Design the programmable frequency divider by method of full custom. It reduces elements as much as possible and meets the different requirements in the frequency of output clock.The CPPLL is completed in SMIC 0.35um CMOS process with 5V supply voltage, the area of the chip is 502μm×476μm. Simulation results show that the PLL can operate from 2MHz to 60MHz. When the output of VCO is 20MHz, the lock time of the PLL is 12.7μs, the peak-to-peak jitter is less than 512ps, and its power dissipation is only 6.2mW, so it can fully saitisfy the requirements of the DSP clock system.At the end, this thesis creates the Verilog function model of the CPPLL in order to meet the demand of DSP system verification, and briefly presents the design of PLL IP core in future work.更多还原