【作者】 马晓旭；

【导师】 叶水驰；

【作者基本信息】 哈尔滨工业大学 ， 微电子学与固体电子学， 2007， 硕士

【摘要】 系统级芯片(SoC: System on Chip)的不断发展,在推动微控制器(MCU)、数字信号处理器(DSP)、微机械电子系统(MEMS)的发展的同时,也推动了嵌入式模数转换技术的发展。作为自然界模拟信号与计算机可处理的数字信号的交互界面,嵌入式ADC涉及到通信、交通运输、医疗设备、数据采集系统、工业工程控制等诸多方面,成为嵌入式系统不可或缺的重要模块之一。为了满足嵌入式系统对ADC的面积小、功耗小、易实现等要求,本文采用逐次逼近型电路结构,设计了一款10位8通路输入的模数转换器,设计整体分为模拟与数字两个子系统,模拟子系统包括模拟多路复用器、缓冲放大器、偏置电路、比较器、复合型DAC。其中,缓冲放大器采用轨至轨输入的电压跟随器结构,使其可在电源电压至地的范围内对信号进行无误差传输;比较器采用三级级联、自动较零的高速比较器结构,不仅实现了高增益,还减小了传输延迟,其比较精度为3mV;DAC采用了电阻分压及电荷分配相结合的复合结构,其中高七位采用等值电阻分压结构,低三位采用电荷分配结构。这种分段复合的结构不断避免了大电容引入的匹配性问题,还缓解了由于制造工艺带来的电阻误差所引起的精度下降问题。数字子系统包括逐次移位寄存器、状态机及时序控制逻辑,其中逐次移位寄存器为系统提供二进制逐次逼近算法;状态机根据需要,控制系统在系统空闲、缓冲放大器采样、缓冲放大器旁路采样、逐次逼近转换四个工作状态下工作;时序控制逻辑则根据系统的不同工作状态,来控制系统的工作时序。本设计由双电源供电,其中模拟电压为3.3V,数字电压为1.8V。电路版图采用和舰公司的0.18μm工艺完成了关键模拟子电路的版图设计。更多还原

【Abstract】 The development of SoC(system on chip) promote the technology progresses of MCU, DSP, MEMS as well as the embedded analog-to digital converters. As the interface of analog signal in the nature and the digital signal that the computers can handle, embedded ADCs are involved in areas of communication, transportation, medical equipments, data acquisition systems industrial process control and so on. Embedded ADCs are already become a indispensable part of SoC.Consider the demand of small area, low power, easy to implement from SoC, design and implement of an 8-channel 10-bit ADC is described in this paper. Successive Approximation Register (SAR) is the configuration adopted. The whole system is divided into two parts: analog sub-system and digital–sub-system. The analog sub-system is consists of analog multiplexing, buffer amplifier, bias circuit, comparator and compound DAC. There into, buffer amplifier is applied of Rail-to-Rail structure, it can track the input signal from power supply to ground potential; Comparator used three-state, automatic zero, high-speed structure, it can not only achieve a high gain, but also reduce the transmission delay; A structure of equal-valued resistors and rationed capacitors assembled is adopted in DAC implement, which avoids the mismatch of big capacitors and the linear error caused by application of resistors. The digital sub-system is consists of SAR, which applied the dichotomy arithmetic; state machine, which controls the whole system to work among the states of SM_IDLE, SM_BUF, SM_FINAL and SM_CONV; the timing logic, which control the timing in different states. The power of analog sub-system is 3.3V, and the power of digital sub-system is 1.8V. Layout of analog part is full custom designed through 0.18μm technology of HeJian Company.更多还原