【作者】 李跃峰；

【导师】 王丹；

【作者基本信息】 西南交通大学 ， 微电子与固体电子学， 2008， 硕士

【摘要】 SPI(Serial Peripheral Interface,串行外围接口)是Motorola公司提出的外围接口协议,它采用一个串行、同步、全双工的通信方式,解决了微处理器(或者微控制器,嵌入式微处理器)和外设之间的串行通信问题,并且可以和多个外设进行直接通信,具有配置灵活,结构简单等优点。Wishbone总线是Silicore公司推出的片上总线协议,它的结构极其简单、灵活,又完全公开、完全免费,获得众多支持。随着SOC(System On Chip,片上系统)的发展,其设计中需要可复用的IP(Intellectual Property,知识产权)核,因此本文主要内容是用Verilog HDL语言对基于Wishbone片上总线的SPI接口电路进行RTL(Register Transfer Level,寄存器传输级)描述,并在EDA(Electronic Design Automatical,电子设计自动化)平台上对其进行功能的验证和仿真,以此来讨论可复用技术在现代集成电路设计中的应用,并设计面向SOC,便于SOC调用的具有可复用性和实用性的SPI IP核,从而实现SOC通过SPI接口与外围设备的通信。在设计中,本文将程序层次化,完成了spi_master和spi_slave的设计,并且编写了测试程序testbench,检测串并转换之后wishbone_master与spi_slave之间数据传输的正确性,通过软件仿真,来验证其功能的正确性。最终本设计达到预期目标和SPI通信要求,spi_master可以作为一个独立的可重复使用的IP核,被SOC调用。之后,本文还将从功能、速度、面积、成本等方面对本次设计进行分析,以此总结集成电路设计中获得的经验。更多还原

【Abstract】 The SPI put forward by Motorola Company is a full-duplex, synchronous, serial data link that is standard across many microprocessors, microcontrollers, and peripherals. It enables communication between microprocessors and peripherals and/or inter-processor communication. The SPI system is flexible enough to interface directly with numerous commercially available peripherals, and it also has some excellences such as it can be configured flexibly and it has a simply structure, and so on. Wishbone bus is a On-Chip-Bus protocol released by the company of Silicore. Its structure is very simple, flexible, and it’s completely public, completely free, so it acquires numerous supports. Along with the development of System-On-Chip, its design needs reusable IP Core. So this article mainly introduces particularly how to describe the SPI with Verilog HDL in RTL’s level, then simulate and verify it with EDA softwares. After then, we probe into the Reusing Methodology’s application in modern circuit system. At last we finish a reusable SPI IP core based on Wishbone bus for SOC, to accomplish the correspondence between SOC and peripherals through the SPI. In the design, programme is hiberarchy, and the spi_master’s design and the spi_slave’s design are finished in this paper, and also have a testbench programme to check SPI function. Finally, the design achieves the expectant target and the SPI protocol’s requirements, and the spi_master module is a independent, reusable IP Core for SOC. Then, this text will carry on the analysis to this design from the aspects, such as function, speed, area and cost and so on, and sum up experiences that acquired in the integrated circuit design.更多还原