【作者】 廖裕民；

【导师】 余宁梅；

【作者基本信息】 西安理工大学 ， 微电子学与固体电子学， 2008， 硕士

【摘要】 视频压缩技术一直是视频处理领域的一门关键技术,也一直是研究的热点。随着多媒体技术和网络的发展,人们对于视频压缩及实时传输的要求也不断提高。矢量量化(VQ)是一种简单高效的图像压缩算法,同时其算法结构简单,适合于硬件实现。同时,运动估计作为一种常用的视频编码技术,可以用于消除视频序列中的时间冗余。因此,如果将矢量量化和运动估计相结合,即在视频编码中,静态帧编码策略为矢量量化,而动态预测帧的编码策略为运动估计,就可以将两者的优势相结合,在保持图像质量的基础上进一步提高压缩率。首先,在视频编码的静态帧方面,提出了一种基于旋转压缩码书的矢量量化算法(VQ),并设计了硬件结构。该算法充分利用了码书之间方向上的相关性,将各个码书旋转后进行压缩存储,编码时将旋转压缩码书恢复后进行编码,从而大幅降低了需要存储的码书数量。在硬件实现时相较于典型的矢量量化算法减少了75%的存储空间和75%的输入带宽,而PSNR平均只降低0.28dB。其次,在视频编码的帧间预测编码方面,文章设计了一个全搜索运动估计模块结构,并讨论了其低功耗实现。之后又继续分析讨论了一些快速运动估计算法,如对角线匹配策略的运动估计算法和菱形搜索运动估计算法,并针对这些算法设计了相应的硬件结构。最后,由于课题组已经在传统矢量量化算法的基础上,开发了一种快速矢量量化算法PDVQ算法,并且设计完成了PDVQ芯片。因此,在已有的成果基础上,设计了一个基于PDVQ的视频编码系统的实现方案,该结构采用了前面提出的全搜索运动估计结构,在提高计算速度的同时极大的减少了输入数据带宽,最终的系统性能良好,在提高压缩率的同时基本保持了图像的编码质量。最终,本文使用硬件描述语言Verilog对提出的结构进行RTL级代码编写,并基于Charter标准单元库的0.35um CMOS工艺实现,采用Synopsis Design Compiler进行综合,后仿功能正确。为了进一步验证其功能,将所有设计下载到FPGA中,最终的实际测试结果正确。更多还原

【Abstract】 Video compression always is the key technology in the video processing field. As the development of multimedia and network, the requirement for the real-time video compression enhances at the same time. Vector Quantization (VQ) is a simple and effective algorithm which has simple architecture and easy implementation, and it also has high processing speed, therefore, it is very appropriate for real-time video compression application. Motion Estimation (ME) is another video coding technology which attempts to effectively use the temporal redundancy between successive frames. Therefore, if VQ and ME are combined in video coding algorithm, it will keeps the image performance and also has high compression ratio in implementation.Firstly, in the infra-frame coding, a vector quantization (VQ) algorithm based on rotating compressed codebook and its implementation is proposed. The algorithm compresses the original codebook by taking advantage of the original codebook directional correlation, and resumes the original codebook by rotating in the encoding. Compare with the typical vector quantization algorithm, the algorithm decreases 75% memory room and 75% I/O bandwidth but lost only 0.28dB PSNR.Secondly, in motion estimation algorithms, a low-power full search motion estimation unit is proposed. And some fast motion estimation algorithms, such as diagonal matching and diamond search algorithm, are disused in the paper, and the implementations also are designed.Thirdly, the project team has developed a PDVQ chip with PDVQ algorithm, therefore, based on the existent research foundation, a PDVQ based video coding system is proposed. The system can increase the speed and reduce the I/O bandwidth, and also can increase the compression ratio while keeping the reconstructed image quality.Finally, the architecture presented in this paper has been described in Verilog RTL code and synthesized by Synopsys Design Compiler with Charter 0.35um standard cell library, and the result of gate-level simulation is correct. For verify the function, all the designs are downloaded into FPGA, and the waveform in the logic analyzer also is right.更多还原