基于CMOS工艺的射频功率放大器的设计

【作者】 于海燕；

【导师】 吴明赞；

【作者基本信息】 南京理工大学 ， 电路与系统， 2008， 硕士

【摘要】 这篇论文以射频发射机末端的功率放大器为研究对象,根据无线局域网的802.11a标准,应用Agilent公司的ADS电路仿真软件,进行功率放大器的设计与模拟。首先,在系统分析功率放大器的结构、设计原理、性能指标的基础上,根据功率放大器的应用背景,选择A类放大器进行设计。设计时综合多种因素,合理选用共源共栅结构和共源结构的三级差分放大电路,进行增益和输出功率分配,然后应用ADS软件进行设计、优化和仿真。仿真结果为:在1.8V的电源电压条件下,输出功率Pout在P1dB点为21.7dBm,输出饱和功率大约为23.5dBm,在5.2GHz处,正向传输系数S21达到25.4dB,输出三阶互调量为29.5dBm。功率增加效率PAE最大为29%,静态工作电流为810mA。输出结果表明,设计的功率放大器在其工作频率范围绝对稳定,实现了很好的输入输出匹配,具有较好的线性度和隔离度,最终的仿真结果满足802.11a标准。其次,针对三级放大器级数多、效率较低、集成度不高的缺点,提出了一种改进的二级功率放大器的设计,改进的措施主要包括设计无源螺旋形电感、合理运用Cascode电感接入、改进偏置电路的设计。仿真结果为:P1dB点的Pout为18dBm,输入输出匹配的情况下,功率增益为30dB,1dB压缩点的PAE为16%,输出三阶交调点IP3是26.8dBm,静态工作电流为252mA。结果表明,改进的功率放大器各项性能指标达到设计要求。最后进行功率放大器的版图设计。根据深亚微米CMOS工艺的特点,将已设计和仿真好的功率放大器,采用TSMC 0.18μm CMOS工艺元件库,应用Cadence软件画出版图。上述工作对射频电路的设计有一定的参考价值。更多还原

【Abstract】 This paper presents the design of Power Amplifer,the key component in the end of RF transmitter.According to the Wireless LAN 802.11a standard,the Power Amplifier is designed and simulated with the ADS circuit simulation software of Agilent.First of all,on the basis of analyzing power amplifier’s structure,design principle and performance,according to the application of power amplifier background,select the Class A amplifier to design.By applying synthesizing a number of factors,select third-stage differential amplifier of cascode structure and co-source structure reasonably,to distribute gain and output power.Then use ADS software to design,optimize and simulate.The simulation results are:under the conditions of 1.8 V supply voltage,the output power Pout is up to 21.7 dBm at P1dB compression point,saturated power output is about 23.5 dBm.at 5.2 GHz.positive transmission coefficient S21 reaches 25.4 dB,the output point of third-stage intermodulation is about 29.5 dBm.The Power-Added Efficiency PAE is about 29%at saturation point.Static work current is about 810 mA.The output results show that the power amplifier in the frequency range has absolute stability,reaches a very good input and output match,obtains good linearity and isolation,the ultimate simulation results meet 802.(?)a standard.Secondly,aim to low efficiency,low integration and more stages of the third-stage Power Amplifier,a second-stage Power Amplifier is bring forward to ameliorate these shortcomings,The measurements includes the design of passive spiral inductor,rational use of Cascode inductors,improving the bias circuit design.The simulation results are:the output power Pout is 18 dBm in P1dB point,in the condition of input and output match,the power gain is 30 dB at 5.2 GHz,the PAE at 1dB compression point is 16%,the output of IP3 is 26.8 dBm,the total static work current is about 252 mA.These results indicate that the performance of improved Power Amplifier meets the design requirements.Finally,execute the design of layout.According to the characteristics of CMOS technology in Deep Submicron,by using TSMC 0.18μm CMOS technology library and Cadence software,draw the layout of the Power Amplifier circuits that have been completing design and simulation.These above jobs have certain value to the work of the RF circuit design.更多还原