【作者】 梁红松；

【导师】 窦建华；

【作者基本信息】 合肥工业大学 ， 电路与系统， 2008， 硕士

【摘要】 在卫星导航接收机中,系统的解调性能直接影响到接收机是否正常工作。系统解调性能的关键因素是参考载波信号同步提取。在同步通信系统中,“同步”是进行信息传输的前提。为了保证信息的可靠传输,同步系统应该有更高的可靠性。性能较差的同步系统,将影响整个通信系统的正常工作。所以研究影响载波同步性能的因素、实现性能优良的载波同步系统,具有重要的意义。本文对载波同步系统性能进行了分析,并研究了适合卫星导航接收机载波同步系统的具体结构。考虑到载波同步系统的运算精度,硬件资源的使用,功耗以及运算速度等方面的性能,本文对载波同步系统中的数控振荡器(NCO)和低通滤波器进行了改进。NCO采用坐标旋转数字计算(CORDIC)算法,可有效地提高同步系统的运算精度,减少使用资源。混频器采用Booth乘法器实现,在保证了运算速度的同时减少了占用的硬件资源。低通滤波器采用具有抽取和低通功能的级联积分梳状(CIC)抽取滤波器,引入非递归结构和COSINE滤波器来改善其旁瓣抑制比并具有较低的硬件结构复杂度。该系统已通过前期仿真,并用VerilogHDL语言设计和实现。更多还原

【Abstract】 In the satellite navigation receiver, the system’s demodulation performance directly affects the receiver normal working. In demodulation system, the reference carrier synchronization performance affects the demodulation system’s. In synchronization communication system, synchronization is the premise of information transmission. In order to ensure the information transmit reliably, synchronization system should have a higher reliability, and the poor performance synchronization system will make the entire communication system work not well. So it is important to research and realize the excellent performance carrier synchronization system.Though anglicizing the carrier synchronization system theory, researching the structure that is suitable to Satellite Navigation Receiver. The paper mainly improves the NCO (Numerically Controlled Oscillator) and CIC (Cascaded Integrator Comb) Low-Pass Filter’s structure to make the carrier synchronization system have better performance. NCO is designed using CORDIC(Coordinate Rotation Digital Computer)algorithm, and a narrow angle mapping technique has been proposed and described concisely. In contrast with the NCO based only on look-up table, its advantage is much less resource consumption; In contrast with the NCO based only on CORDIC algorithm, its advantage is shorter pipeline. The NCO design using Narrow Angle Mapping Technique could enhance operational precision, provides higher speed operation, lower power waste. Booth multiplier is used to ensure the high operation speed while reducing the consumption of hardware resources. A modified CIC decimator filter structure is proposed. The magnitude response of the filter is improved by using cosine prefilters, the complexity of the filter is reduced by using non-recursive parallel structure and it is steady. At last, the system is designed by VerilogHDL.更多还原