【作者】 张建生；

【导师】 高明伦； 胡永华；

【作者基本信息】 合肥工业大学 ， 检测与自动化装置， 2008， 硕士

【摘要】 ITRS预计到2010年时半导体工艺技术将进入45纳米阶段,单个芯片可以集成数十亿计的晶体管。基于这种技术发展的趋势,单台PC机的全部电路(显示器和键盘除外)都可以集成到一块芯片实现单芯片计算机。本论文工作围绕基于8086的单芯片计算机最小集项目开展研究,采用IP/SoC的设计方法,设计了最小集中两个重要的外设IP电路—可编程外围接口IP与可编程外围定时/计数器IP,并实现了这两个IP分别与8255和8254芯片指令集兼容,最后实现了两个IP在单芯片计算机平台中的集成验证。为了增加整个芯片平台的可测性与可调试性,本论文讨论了目前流行的边界扫描测试技术,设计了边界扫描测试电路—JTAG调试模块,增强了芯片的可测试性与可调试性。实验结果显示,两个外围IP与JTAG调试模块都能很好的满足设计的要求。主要工作和取得的成果如下:1)探讨了一种基于8086 CPU核的单芯片计算机平台的架构,设计两款外围接口IP软核a8255和a8254,并对其进行IP独立验证,实现基于8086单芯片计算机平台的最小集搭建;2)设计基于IEEE 1149.1标准的JTAG调试模块,为单芯片计算机提供测试与调试端口。更多还原

【Abstract】 ITRS expected that semiconductor technology scale would enter 45-nanometer era in the year of 2010 and more than one billion transistors would be integrated into a Single chip.According to this trend,all circuit modules(except monitor and keyboard)of single PC can be integrated in a chip,which is the single-chip computer.The research in this thesis is based on the project of the minimum set of 8086-based Single-Chip PC.In this paper the author adopted the IP/SoC design methodology and designed two important peripheral IPs-programmable peripheral interface a8255 IP and programmable peripheral interval timer a8254 IP.These two IPs are fully instruction-level compatible with 8255 chip and 8254 chip.Then the integration verification of them into a single-chip computer platform is realized.In order to increase testability and debuggability of the platform,this paper also discussed boundary-scan technique and designed the boundary-scan circuit-JTAG debugging module.The experimental results show that both the two peripheral IPs and JTAG debug module can well meet the design requirements.The main work and achievements are as follows:1)A kind of 8086 CPU-based single-PC platform architecture is discussed and design of two peripheral IP cores a8255 and a8254 are implemented.Independent functional verification of them and it integration into the minimum set of Single-Chip PC platform is also discussed;2)Design of JTAG debug module based on IEEE 1149.1 standard is presented to afford test and debug interface for Single-Chip PC.更多还原