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基于FPGA的关节伺服控制器容错技术研究

Research on the Fault-Tolerant Technology of the Joint Servo Controller Based-FPGA

【作者】 党崇伦

【导师】 孙汉旭; 贾庆轩;

【作者基本信息】 北京邮电大学 , 机械设计及理论, 2008, 硕士

【摘要】 随着计算机技术和大规模集成电路的飞速发展,伺服控制器在提高性能的同时也增加了复杂性,给系统的可靠性设计带来了新的挑战。对应用于特殊环境下的控制器而言,如何在有限资源的条件下最大限度地实现容错,同时又能达到所要求的性能,是我们所面临的问题。本论文根据六自由度机器人关节伺服控制器的可靠性要求,对其容错技术进行了研究。首先分析了系统冗余结构的基本类型,并运用马尔科夫模型对各冗余结构的可靠性进行了计算研究,并据此提出了一种双机动态冗余容错的系统设计方案。同时,以NMR结构解决关键部件造成的单点故障的问题,并设计了一种用于NMR的自重构自校验表决电路,在提高冗余部件利用率的同时增加了校验机制,并避免引入外部的信号增加设计复杂度。最后,本文给出了控制器的硬件研制过程。并借助模块化关节测试平台对系统在多种故障情况下的容错性能进行了验证。本系统采用FPGA作为中央控制器件,利用Vorilog语言将相关容错策略以硬件电路的方式实现。并借助NIOSH软核和SOPC技术,将电机控制模块、容错电路等集成于FPGA芯片中,不仅以硬件代替软件的方式降低了故障率,还在实现系统高度集成化的同时提高了其可靠性。本课题的完成,为长寿命、强实时性控制器提供了一个容错度和容错效率都较高的设计方案,该方案能适应特殊环境下的控制和容错的性能要求,具有较广泛的应用价值。

【Abstract】 With the rapid development of computer technology and large-scale integrated circuits, the increasing complexity in the design of controller bring new challenges to the reliability of the system while improving performance. As to the joint controller of robot, how to realize maximum fault-tolerant ability under limited resources and a demanded performance at the same times will be the topic disussed in this paper.This paper studied the fault-tolerant technology under the reliability requirement of the joint controller in 6-DOF robot. It analyzed the basic types of redundant structure, and studied the reliability of redundant system using Markov model, presented a solution of the dynamic dual-controller redundant fault-tolerant system. At the same time, this paper solve single point fault on system with NMR system. And designed a multi-mode redundant self reconstructing, self check judge circuit to realize critical part’s fault handing, avoid introducing extern signal flexibility. Finally, it gave specific circuits for the peripheral design of controller, and validates the fault-tolerant performance of system under various fault conditions with modular joint test platform.The system use FPGA as the central controller and achieve fault-tolerant strategy to hardware circuit with Verilog. It integrates motor control unit and related fault-tolerant strategy in an FPGA chip with NIOSΠsoft core and SOPC technology, using hardware instead of software method to reduce system fault probability, the system get a high reliability and integrity.The achievement of this project provides a high fault-tolerance and efficiency solution which has a certain extent of application value to the design of long-life and hard real-time controller, meeting the requirement of control ability and fault-tolerance in the special environment.

  • 【分类号】TP242
  • 【被引频次】9
  • 【下载频次】221
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