【作者】 何世超；

【导师】 郝跃；

【作者基本信息】 西安电子科技大学 ， 微电子学与固体电子学， 2008， 硕士

【摘要】 测试已经成了集成电路设计制造中不可分割的一部分,而且随着集成电路工艺复杂度和设计复杂度的提高,集成电路的测试变得越来越困难,也变得越来越重要。在这种情况下,可测性设计(Design For Test)技术成为解决芯片生产测试问题的主要手段之一,日益引起人们的重视。片上网络(NoC)结构的显著特点是规模巨大和互连通讯复杂。如此大规模的结构其制造故障也会随之提高,这就对其测试提出了更高程度的要求,需要采用合理的测试策略及测试体系来对片上网络进行测试,以节省测试开销。因此研究NoC测试策略及测试体系对解决NoC及未来电路测试难点有重要意义。本文首先阐述了测试的基本概念,简单地描述了故障检测的基本原理以及现有的一些可测性方法。NoC通讯结构的测试分为两部分:路由开关间互连线的测试和路由开关的测试。针对路由开关间互连线的测试,采用MAF测试模型,利用BIST测试法,设计了TDG单元和TED单元,并通过软件进行了仿真和综合。对于路由开关的测试,由于NoC中数据是以报文的方式进行传播,则可以把测试数据封装成报文的形式,通过路由开关在通讯网络中传播,进而对路由开关进行测试。根据报文地址段的不同,测试可以分为两种:单播测试法和多播测试法。最后分析了两种方法的测试时间。然后本文针对NoC中资源网络接口的多时钟域问题,设计了异步FIFO,利用软件对其进行功能仿真。并通过插入扫描链和隔离双端口存储器,设计了异步FIFO的测试结构。仿真结果显示,插入扫描链后电路的面积和功耗有少量增加。最后本文对NoC测试技术的未来发展方向进行了展望。更多还原

【Abstract】 Testing is a necessary part of the IC design process. Due to the continuous increase in the complexity of IC design and process, design for test(DFT) technology is being more and more diffcult as well as important. And system-on-chip(SoC), which embraced various reused IP cores, makes the testing even more prominent. Now the chip design has developed SoC into NoC which is the communicating of multiple SoC. There are large number of transistors and more complex functions in a single chip. In addition under the pressure of market, we must decrease the design period and use a mass of IP cores in design. So NoC architecture has characteristics of large scale and complexity of communication. But the faults during manufacturing become more difficult to test in large scale architecture.We must research advanced test measure, that is using feasible measure and structure in the testing of NoC to reduce the cost of testing. Thus it is significant to research the test measure and the structure of NoC and even future circuits.In this paper, the conception of DFT is displayed firstly and some conventional test methods are showed.The test of NoC communication structure is divided into two parts: the test of inter-switch links, and test of switchs. We use the MAF model and BIST method to test the inter-switch links. The TDG unit and TED unit are designed, simulated and synthesized in this paper. Because datas are transmitted in the form of packets, we can test the switchs with the test packets composed of test datas. This paper proposes two different strategies for implementing the test: sequential test strategy and multicast test strategy. Then we analyze the test time of two strategys.A kind of two clocks asynchronous FIFO is designed, which is used to resolve the metastability with communication between different clock regions. This paper insets a scan chain and isolates the dual ports memory, and designs the test structure. The result shows that the area and power of the circuit exhibits a little increase.Finally, the paper looks forward to the NoC test technology.更多还原