【作者】 张静波；

【导师】 戴显英；

【作者基本信息】 西安电子科技大学 ， 电力电子与电力传动， 2008， 硕士

【摘要】 RS(Reed-Solomon)码因其具有优良的纠突发错误和随机错误的能力,而被广泛用于数据传输和存储系统中。本文在研究RS码的理论和分析DVD标准的基础上,对算法实现、电路结构、流程控制等进行了优化,给出了一种基于DVD应用的全程流水线纠错纠删RS-PC译码器芯片的VLSI设计。该RS-PC译码器芯片的特点是全程流水线实现,面积小,速度快,纠错能力强,可纠错和纠删,时序控制简单,电路实现简洁,并有较好的扩展能力。该芯片可对DVD数据在存储和读取中引入的错误进行纠错处理,也可作为IP核,用于DVD伺服控制芯片的设计和实现。本文提出的流水线处理的纠错纠删RS-PC译码芯片主要模块包括行RS(182,172)译码器、列RS(208,192)译码器和数据块缓冲管理器。在译码器的设计中,采用修正的欧几里德(ME)算法,并将其优化,降低了设计的复杂度,实现了能够同时纠错和纠删;采用三级流水线结构,使RS译码处理速度达到每时钟一个符号;采用模块复用的设计思想实现关键方程的求解,达到面积优化和电路规整。在数据块缓冲管理器的设计中,采用一种基于二维数据重排的访问方式,实现高速高效的DRAM访问。在RS-PC译码器芯片的顶层,采用外接DRAM的缓冲管理器,实现全程流水线处理的RS-PC译码器,提高了译码的运算速度,达到RS-PC译码速度每时钟一个符号。本文在DVD标准的基础上,定义了RS-PC译码器设计流程;为验证采用的算法和产生的测试数据,设计了RS-PC编译码器的Matlab模型;采用Verilog HDL实现译码器芯片的电路硬件描述,同时进行了功能仿真与时序验证,并进行了FPGA实现。功能仿真与时序验证的结果表明,该RS-PC译码芯片的设计满足预期的性能要求:处理速度达到每时钟译码一个接收符号;在纠错能力上:行纠错能力达到纠正5个错误或10个删除,列纠错能力达到纠正8个错误或16个删除;外接100MHz的SDR DRAM,可实现译码数据吞吐率40Mbytes/s,达到12×DVD的处理要求。更多还原

【Abstract】 RS (Reed-Solomon) code has been widely employed in data transmission and storage systems owing to its excellent capability for correcting burst errors and random errors. Based on the research of RS code theory, analysis of DVD specification, and optimization improved from algorithm, this paper presents a full-process pipelined Errors-and-Erasures correcting Reed-Solomon Product-Code (RS-PC) decoders chip for DVD application. It features full-process pipelined, high-speed decoding, high performance correcting, simpleness of control timing, succinctness of circuit implementation, area efficient, and with good extend capacity. It can correct errors-and-erasures introduced in the process of storage and recovery of DVD data and also can be used as an IP core in the design of DVD servo chip.The main module of the RS-PC decoder chip are two pipelined Errors-and-Erasures correcting RS decoders and a block buffer manager. The RS decoder features an area-efficient key equation solver using a modified Euclid algorithm, which reduced the complexity of the design. Based on the methods of modules reuse, the proposed RS decoder are very regular and area efficient. Using three stage pipelines, the RS decoder can operate at a rate of 1 byte/clk. Based on a method of 2 dimension data rearrange, a high speed and high efficiency implementation of DRAM access is proposed in the design of block buffer manager. Using the block buffer manager with off-chip DRAM, a (182,172) row RS decoder and a (208,182) column RS decoder can be pipelined, which double the speed of RS-PC decoder and get a rate of 1 byte/clk.Based on the DVD specifications, the RS-PC decoder chip design is defined. The Matlab model of RS-PC encoders and decoder is presented for the verification of the algorithm. The hardware of RS-PC decoder chip is described in the Verilog HDL, function simulation and timing verification are processed, and then is implemented in a Altera FPGA. Through the function simulation and timing verification, the proposed RS-PC decoder meet the expected performance requirement, which gets the rates of one byte per clock, gets the max row error correcting of 5 errors of 10 erasures and the max column error correcting of 8 errors or 16 erasures, gets a data rate 40Mbytes/s interfaced with 100MHz SDR DRAM, which meet the 12×DVD performance requirement.更多还原