通道均衡在宽带数字阵列雷达中的技术研究

【作者】 陈刚；

【导师】 何子述；

【作者基本信息】 电子科技大学 ， 信号与信息处理， 2008， 硕士

【摘要】 宽带数字阵列雷达是采用宽带信号波形、发射和接收都使用数字技术和波束形成技术的阵列天线雷达。其相对于传统相控阵来说,具有巨大的优势:易于实现超低副瓣,大的动态范围,波束扫描速度快,可同时多波束等。然而宽带数字阵列雷达阵列通道中的模拟器件及其构成的电路特性的差异会使多个发射通道和接收通道产生随频率变化的幅度和相位特性的不一致,即通道失配。通道失配会严重影响宽带数字阵列雷达所具有的优越性能。本论文针对这一问题,分析了通道失配对雷达性能的影响,重点研究了宽带数字阵列雷达中的补偿通道失配的通道均衡技术。首先从理论上推导了通道失配对数字波束形成以及脉冲压缩的影响。给出了FIR扰动模型,并通过仿真实验表明,不论是通道幅度失配,相位失配或者幅度相位均失配,通道失配对低旁瓣波束形成影响都非常大。工程上,为了得到低旁瓣波束需要精确地控制雷达通道在整个波形带宽内的频率响应。然后研究了通道均衡的时域算法和频域算法。通道均衡的时域算法是基于维纳滤波理论和最小二乘理论,文中给出了时域均衡的基本算法,并基于给出的IIR零极点扰动模型进行了仿真。本论文重点讨论了通道均衡频域算法,并对基本算法作了适当的修正即采用加权的最小二乘拟合法,并且把参考通道幅度响应作为加权矩阵的对角元素,获得了更好的均衡性能。此外,还详细分析了通道频率响应的失配程度、校正信号信噪比、均衡器抽头数、带宽时间延迟积、FFT点数M等因素对均衡器性能的影响,为以后的工程实现提供了理论基础。为了满足工程应用上计算复杂性和性能之间的折中,我们考虑在一定的条件下,用传统的窄带校正的方法来替代均衡。通过仿真实验,可以看出在对带宽、通道失配程度、BT值有一定约束时,以校正来代替均衡能够在减小计算量的情况下取得良好的性能。最后,给出了通道均衡器在数字阵列雷达中的实现方案以及接收通道和发射通道的均衡器实现框图和流程。由于均衡器是复数的FIR滤波器。但是FPGA中只能实现实数FIR滤波器,因此在结构上,可以用四个FIR实数滤波器等效一个复数FIR滤波器。FIR滤波器的主要组成模块是乘/加单元(MAC),如果按照直观结构构造乘法器和系数寄存器来实现会占用大量的逻辑资源,显然不可取。因此考虑用分布式算法以利用FPGA高并行度的结构特点,同时利用整数最优表示法与离散化方法来对FIR滤波器的二进制系数作优化,在保证运算速度的前提下,进一步降低逻辑资源的消耗。更多还原

【Abstract】 Wideband Digital Array Radar (WDAR) is a fully digitized array antenna radar in which wideband signal waveform is transmitted and digital beam forming (DBF) technology is used in receiving and transmitting. Compared with conventional phased array radar, it can offer significant advantages. Such as low side lobes, high dynamic range (DR), rapid multi-beams steering, etc. But the change in the characteristic of analog devices and circuits in the element channels will cause the frequency-dependent amplitude and phase difference of receiver channels and transmitter channels in WDAR. The differences among the frequency responses of the channels are called channel mismatch. Channel mismatch will affect the superior performance of the WDAR seriously.In this thesis, the impact of the mismatch on WDAR’s performance is analyzed. Adaptive channel equalization in order to compensate for the channel mismatch is investigated.First of all, the impact of channel mismatch on DBF and pulse compress is analyzed. The simulation based on FIR mismatch model is given. It shows that impact of mismatch on low-sidelobe beams is serious. Therefore, the real project requires precise control of the radar receiver’s frequency response across the entire signal waveform bandwidth.Two channel equalization algorithms, named frequency-domain based and time-domain-based algorithms are investigated for compensating the channel mismatch. Channel equalization time-domain-based algorithm is based on Weiner filter theory and Least Squares theory. Basic algorithm of the time domain equalization is presented. And simulation based on IIR mismatch model is given. Frequency-domain based channel equalization algorithm is investigated mainly which is based on least squares fitting method. A modified method is presented which is weight least squares fitting method, and the diagonal elements are the reference channel magnitude response. Good equalization performances are achieved by using the improved method. Impacts of many factors on equalization performance are analyzed. Such as the mismatch extent of frequency response of the receive channel, SNR, the length of equalizer L, Bandwidth-Time delay product, FFT-points. All of these factors have references to real project.To satisfy the request of less computation and better performance in real projects, calibration is considered to replace equalization to some extent. The simulation is given. It showed that calibration may achieve high performance with some restriction of the mismatch extent of frequency response, SNR, Bandwidth-Time delay product, equalizer length L, FFT-points M, etc.Finally, the blue print of channel equalizer in WDAR is presented. The Flow of equalizer of both receiving and transmitting is described. For the coefficients of FIR filter in Matlab are complex number, but they can’t be implemented in FPGA. So the structure of FIR filter is modified in which four real FIR filters substitute for one complex FIR filter. FIR filters consist of MAC mainly. It’s wasteful and inefficient that FIR filters are simply constructed by multiplications and coefficient registers. So the Distributed Arithmetic which coverts the multiplications into some look-up operations is presented. In this thesis, an improved optimum representation of integer coefficient and a discrete coefficient method is introduced according to the FPGA structure. It can assure the decrease of hardware logic resource and the increase of compute performance.更多还原