Nios系统中Avalon从外设（PWM）的设计和研究

【作者】 杨小明；

【导师】 赵建军；

【作者基本信息】 昆明理工大学 ， 物理电子， 2008， 硕士

【摘要】 Nios处理器是一种在单芯片上的CPU,其外围集成了存储器和外部设备。其特点类似微控制器或单片机。但与固定式微控制器不同,Nios处理器是一种可配置的软核处理器,“可配置”意味着其构建的系统,其性能或功能可以根据用户要求进行增减以满足性能或价格的要求。“软核”则意味CPU的核心是以软件设计的形式提供,并可下载到Altera公司的FPGA可编程芯片中,而不是传统的、不可修改的硅芯片形式。换句话说,Altera公司从不出售Nios芯片,Altera公司只出售空的FPGA芯片。由用户对软件形式的Nios处理器代码以及外部设备进行修改和配置,最终符合特定要求,然后再将系统下载到Altera公司的FPGA芯片中。Altera公司提供了一套用于Nios处理器的通用外部设备,例如时钟、串行接口、通用I/O口、SDRAM控制器和其他存储器接口。设计人员也可以创建自定义的外部设备并将其集成到Nios处理器系统中。对于一个要求CPU执行某些特定代码的性能要求很高的系统,通常可以创建一个具有类似功能的自定义外部设备的硬件来取代这部分软件。由于硬件的工作速度远远超过软件的工作速度,这将使系统的性能大幅度提高,而且在自定义的外部设备处理数据时,还可以让CPU有更多时间去处理其他任务。本文以Nios嵌入式软核为基础平台,以PWM的设计为例,介绍用户自定义的基于Avalon的从外设元件的设计方法和过程。重点论述了Avalon总线的一些基本特性,以及如何设计从外设的底层硬件和软件驱动程序,并提供了外设的API接口函数,在此基础上编写了用户的高层控制程序。该设计在FPGA上完成并得到正确结果。对嵌入式系统开发和基于IP核的设计有一定指导意义。更多还原

【Abstract】 A Nios system is similar in traditional microcontroller or "computer on chip", because the Nios system contains peripherals device and memory. But the Nios system is different from other traditional microcontroller or "computer on chip" in many places.The Nios II processor is a configurable soft-core processor, as opposed to a fixed-microcontroller. In this context, "configurable" means that features can be added or removed on a system-by-system basis to meet performance or price goals. "Soft-core" means the CPU core is offered in "soft" design form (i.e., not fixed in silicon), and can be targeted to any Altera FPGA family. In other words, Altera does not sell "Nios II chips"; Altera sells blank FPGAs. It is the users that configure the Nios II processor and peripherals to meet their specifications, and then program the system into an Altera FPGA.Altera provides a set of peripherals commonly used in microcontrollers, such as timers, serial communication interfaces, general-purpose I/O, SDRAM controllers, and other memory interfaces. Designers can also create their own custom peripherals and integrate them into Nios II processor systems. For performance-critical systems that spend most CPU cycles executing a specific section of code, it is a common technique to create a custom peripheral that implements the same function in hardware. This approach offers a double performance benefit: the hardware implementation is faster than software; and the processor is free to perform other functions in parallel while the custom peripheral operates on data.This text describes the design flow to develop a custom SOPC Builder component (PWM) based Nios II IP core. Discussed some characteristic of Avalon bus and how to design slave Avalon Interface from hardware to software, at the some time we provided API to transfer by higher custom. Here the foundation is write the customer of high controls procedure. The total design is complete on the FPGA and gets the right result. This text has some guide meaning for embeded system develop and some design based IP core.更多还原