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DVB-S2信道接收芯片载波恢复算法的研究与实现

Researching and Implementation on Carrier Recovery Algorithm of DVB-S2 Demodulator

【作者】 李燕华

【导师】 林平分;

【作者基本信息】 北京工业大学 , 微电子与固体电子学, 2008, 硕士

【摘要】 随着数字通信技术的飞速发展,卫星数字电视系统DVB-S逐渐的被新标准DVB-S2代替,由于国内的数字电视产业相对落后,所以跟踪最新的通信技术十分必要。本论文详细的研究了第二代卫星数字电视系统DVB-S2的载波恢复技术。载波恢复是数字通信系统中解调模块里非常重要的一部分,用于纠正传输信道和接收系统所造成的信号的频偏、相偏和相位噪声。由于载波恢复需要捕获较大的频偏范围、较短的收敛时间、较小的相位噪声和较低的硬件实现成本,所以本文从这四个方面考虑算法的选择。首先将载波恢复模块分成频率恢复环路和相位恢复环路,频率恢复环路用于纠正大的频偏,而相位恢复环路用于纠正剩余的频偏和相偏。分析了五种经典的频率检测器,由于四重相关器和频偏直接检测法能捕获的频偏范围小,而极大似然估计法和差分功率检测法的硬件实现复杂,所以选择了频率捕捉范围足够而且硬件实现方便的导频检测法作为频率检测器的算法。在分析了M阶科斯塔斯环、极型科斯塔斯环、直接判决法三种算法的原理和性能之后,选择了硬件实现简单、性能满足要求的极型科斯塔斯法作为相位检测器的算法,同时,锁定检测器采用了相偏累加法。然后用C语言对算法进行建模,仿真了环路捕获频偏范围、相位噪声、收敛速度等性能指标,仿真结果表明,能捕获至少20%的符号速率的频偏;在频偏为80KHz时,收敛时间是50us。然后根据仿真结果设定了环路滤波器的增益、锁定器的阈值等参数,最后给出了在不同信噪比下,整个环路的误码率,与理论值大约差了0.5dB。在浮点模型完成之后,进行了定点化和RTL代码实现,并对硬件结构进行了优化。最后在FPGA上进行综合,得到了硬件的最高可运行速度是85MHz,占用了硬件资源约为3000个LUT。

【Abstract】 As the communication techniques improves, the satellite digital television system DVB-S will be replaced by the second generation standard DVB-S2. It is necessary to follow the newest communication techniques for the national digital television industry is behindhand.This paper works on the carrier recovery techniques of DVB-S. Carrier recovery is an important part of the demodulator of digital communication systems, and it is used to correct the frequency offset, phase offset and the phase noise caused by the transmission channel and the demodulation.Frequency offset, convergence time, phase noise and hardware cost are the most important factors for algorithm selecting. First, the carrier recovery loop is divided into two parts, frequency recovery loop and phase recovery loop. Frequency recovery loop is used to correct the initial frequency offset and phase recovery loop is used to correct the residual frequency offset and phase offset. Five classical algorithms are studied. Quadricorrector and Direct-Detector can capture small frequency offset range while Maximum-Likelihood and Differential-Power have complex hardware, so Pilot-aided detector is used in frequency recovery loop. And Polarity Costas Loop and Phase Offset Accumulation are adopted in phase recovery loop and lock detector respectively. C language is used to setup the float point model. Performance including frequency offset range, phase noise and convergence speed are simulated. It shows that at least 20 percents of symbol rate frequency offset can be captured, and the convergence speed is 50us when the frequency offset is 80kHz. The loop filter gain and the lock detector threshold are set according to the simulation result. The BER of the whole loop is also present. It’s about 0.5dB worse than the theory. Fixed point model and RTL code are finished, and the hardware structure is also optimized. Finally, the FPGA synthesis shows that hardware’s highest speed is 85MHz, while about 3000 LUTs are utilized.

  • 【分类号】TN851;TN949.197
  • 【被引频次】2
  • 【下载频次】292
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