【作者】 孙彤；

【导师】 李冬梅；

【作者基本信息】 清华大学 ， 电子科学与技术， 2007， 硕士

【摘要】 逐次逼近模数转换器(ADC)具有中等转换精度和中等转换速度,采用CMOS工艺实现可以保证较小的芯片面积和低功耗,而且易于实现多路转换,在精度、速度、功耗和成本方面具有综合优势,被广泛应用于工业控制、医疗仪器以及微处理器辅助模数转换接口等领域。论文工作设计了一个电源电压为2.5V,精度为12位,速度为500kS/s的低功耗逐次逼近ADC。电路采用单端轨到轨输入,并具有省电模式。研究工作主要分为三个部分:①研究设计了一个分段电容式数模转换器(DAC),高端低端各6位,共有128个单位电容,减小了芯片面积,降低了动态功耗,而且高3位采用温度计编码,保证了DAC高位的单调性;分段电容阵列的版图采用共中心的对称布局,以提高电容的匹配精度。②对多级结构比较器进行了研究设计。比较器由三级前置放大器和一级锁存器组成,根据每级前置放大器的位置不同,对它们的增益、带宽、功耗进行了优化,每级前置放大器和模拟缓冲级电路的设计也减小了回程噪声的影响;比较器的设计应用了失调校准技术。仿真结果显示,该比较器可以有效消除10mV输入失调,能够在10MHz速度下分辨0.2mV输入电压,功耗只有600uW,达到了设计要求。③对控制电路进行了研究设计。采用分模块设计方法,使用verilog-HDL描述、自动综合、布局布线生成,能够控制模拟部分完成逐次逼近过程,并可以根据片选信号时间长短控制芯片进入省电模式或者工作模式。论文工作在完成ADC电路设计仿真的基础上,完成了整个电路的物理版图设计、后仿真及芯片的测试。该逐次逼近ADC采用UMC 0.18um混合信号CMOS工艺设计制造,芯片面积为1.4mm×1mm。实测结果显示,在500kS/s下,其SNDR为63.13dB,即ENOB为10.5位,|DNL|小于2LSB,|INL|小于4LSB,功耗为1.2mW。更多还原

【Abstract】 Successive approximation analog-to-digital converters (ADCs) have medium resolution and medium speed, small chip area and low power consumption can also be achieved in CMOS process. Moreover, it is convenient to make multi-channel conversion. Due to their mixed advantages in resolution, speed, power and cost, successive approximation ADCs are widely applied in industry controlling, medical instruments, auxiliary analog-to-digital interfaces of micro-processors and so on.A 2.5V, 12bit, 500kS/s low-power successive approximation ADC is designed in this thesis, which adopts single rail-to-rail input and has power-down mode.Study work can be categorized into 3 parts:①A segmented capacitive digital-to- analog converter (DAC) is designed with 2 separated 6-bit arrays which consist of 128 unit capacitors in all, resulting in smaller chip area and lower dynamic power. Moreover, thermometer coding is applied to the top 3 bits, ensuring the DAC’s monotonicity. Common centroid geometry is introduced in the layout to improve matching property.②A multi-stage comparator is designed, which is composed of 3 pre-amplifiers and a latch. Each pre-amplifier is optimized according to its position, the design of them and the analog buffer has already taken kickback noise into consideration. An offset cancellation technique is applied too. Simulation results show that, the proposed comparator can distinguish 0.2mV input with 10mV offset at 10MHz, while its power is 600uW.③The control circuit is designed in several modules, which is described in verilog-HDL, synthesized, placed and routed automatically. This digital block coordinates analog circuits to finish the successive approximation, and switches the chip into power-down mode or work mode.After circuit design and simulation, the physical layout design, post-simulation and chip measurement are also finished. The proposed ADC is designed and fabricated in UMC 0.18um Mixed Mode CMOS process, occupying 1.4mm×1mm. Measurement results show that, its SNDR achieves 63.13dB at 500kS/s, thus ENOB is 10.5bit, and |DNL| is less than 2LSB, |INL| is less than 4LSB, with overall power only 1.2mW.更多还原