【作者】 梁田；

【导师】 沈海斌；

【作者基本信息】 浙江大学 ， 电路与系统， 2008， 硕士

【摘要】 本论文研究的主要内容是有限域算术、椭圆曲线加密算法和有限域乘法器。椭圆曲线加密算法是目前提供了最短的密钥长度和最优的每比特加密强度的公钥加密算法。而椭圆曲线加密算法的性能取决于有限域运算的速度,有限域乘法运算又是有限域运算中其他运算的基础。这使得有限域内的快速运算尤其是二元括域上的乘法运算成为了近期的研究热点。本文的重点在于有限域乘法及有限域乘法器的算法设计,尤其是由三项式及五项式生成的二元域。考虑到目前信息安全系统的有效性,本文所提出的有限域乘法器结构均为位并行乘法器。本文基于移位多项式基底(SPB)及其弱共轭基底(WDB)的有限域乘法器结构对有限域乘法器的设计实现进行了研究。在由不可约三项式和不可约五项式构建的有限域中,本文提出的架构在相同的空间复杂度下有着目前最小的时间复杂度。而且,本文提出的乘法器结构具有很高的规则性,大大降低了硬件电路设计者对数学知识的要求,为乘法器的快速设计实现提供了极为有利的条件。进一步的,通过verilog硬件描述语言对三项式乘法器设计进行了实现,通过EDA软件Design Compiler,Power Compiler对设计进行了综合及优化、功耗分析及优化。研究得到结论,该乘法器架构在相同的空间复杂度的前提下实现了最低的时间复杂度(最短的关键路径)。不仅如此,该乘法器架构还以其规范性易于通过硬件描述语言实现。更多还原

【Abstract】 The finite field arithmetic, elliptic curve cryptography (ECC) and the finite field multiplier are investigated in this thesis. ECC is the one of the known public crypto arithmetic which provides the smallest key size and the best strength-per-bit The calculation speed over finite field greatly affects the performance of ECC implementation. This fact has inspired many researchers to find ways on performing fast computations over finite fields, especially over large finite fields of characteristic two.The central theme of the thesis is an investigation of finite field computations and their architectures, particularly the irreducible trinomials and pentanomials. All the multiplier architectures proposed in this thesis are bit-parallel finite field multipliers which canimprove the efficiency of cryptosystems significantly.New structures of bit-parallel multiplier based on SPB and its weakly dual basis (WDB) over finite field are presented. To the fields generated by trinomials and pentanomials, the proposed structures have the shortest critical path up to date with nearly the same space complexity. Furthermore, it is easy for a designer to implement the proposed multipliers into hardware for their regular structures.Furthermore, by implemented the proposal of new structure of finite field multiplier using verilog HDL, and analyzing in detail the performance of algorithms in finite field and the performance of the proposal using EDA soft Design Compiler, Power Compiler, we have drawn a conclusion that this proposal structures have the shortest critical path up to date with nearly the same space complexity. Furthermore, it is easy for a designer to implement the proposed multipliers into hardware for their regular structures. We also optimize the power consumption of the proposal structure.更多还原