【作者】 彭成；

【导师】 胡锦；

【作者基本信息】 湖南大学 ， 微电子学与固体电子学， 2008， 硕士

【摘要】 随着集成电路频率的提高和多核时代的到来,传统的高速电互连技术面临着越来越严重的瓶颈问题,而高速下的光互连具有电互连无法比拟的优势,成为未来电互连的理想替代者,也成为科学研究的热点问题。目前,由OIF(Optical Internetworking Forum,光网络论坛)论坛提出的甚短距离光互连协议,主要面向主干网,其延迟、功耗、兼容性等都不能满足板间、芯片间光互连的需要,因此,研究定制一种适用于板级、芯片级的光互连协议具有非常重要的研究意义。本论文将协议功能分为数据链路层和物理层来设计,链路层功能包括了协议原语设计,数据帧格式和数据传输流程设计,流量控制机制设计,协议通道初始化设计,错误检测机制设计和空闲字符产生、时钟补偿方式设计;物理层功能包含了数据的串化和解串功能,多通道情况下的绑定功能,数据编解码功能等。然后,文章采用FPGA(Field Programmable Gate Array,现场可编程门阵列)技术实现了定制协议的单通道模式。重点是数据链路层的实现,物理层采用定制具备其功能的IP(Intellectual Property,知识产权)——RocketIO来实现。实现的过程中,采用了Xilinx公司的ISE(Integrated System Environment,集成开发环境)开发流程,使用的设计工具包括:ISE,ModelSim,Synplify Pro,ChipScope等。最后,本文对实现的协议进行了软件仿真和上板测试,访真和测试结果表明,实现的单通道模式,支持的最高串行频率达到3.5GHz,完全满足了光互连验证系统初期的要求,同时由RocketIO的高速串行差分口得到的眼图质量良好,表明对物理层IP的定制是成功的。更多还原

【Abstract】 With the frequency of integrated circuits improving and multi-core’s coming,the bottleneck of the traditional high speed electronic interconnect technology is more and more serious.Comparing it,optical interconnector have more merits in high speed area,it is an ideal replacer for electronic interconnector in future.also,it is a hot area in scientific reseach.At present,the Very Short Reach(VSR) protocol suggested by OIF,mainly faced to backbone,its delay,power,compatibility etc.is not suitable for board-to-board,chip-to-chip optical interconnector.So reseaching a appropriate protocol for this is significance.In this paper,the function of the protocol was divided into data link layer and physical layer,the former layer contains protocol primitive sets design,the format of data frame design and data transmit flow design,flow control design,the initial mechanism for the protocol channel design,error detect design,idle character generation design and the manner of clock compensation design;the latter include data serialize and deserializ function,lanes bind function,data coding and decoding etc.Then, FPGA (Field Programmable Gate Array) technology was used to implemented the single channel of the protocol,this paper focus on data link layer,and the physical layer introduces an custom-built IP——RocketIO to replace.when implemented,the Xilinx corporation’s ISE development flow was adopted,the design tools included ISE, ModelSim,Synplify Pro,ChipScope etc.At last,through software simulation and on board testing,the results indicate that the max serial frequency reached 3.5GHz when the protocol in single channel,it satisfies the optical interconnected validate system.at the same time,the eye diagram,obtained from the RocketIO’s high speed serial difference ports,is righ,this indicate that the customization of physical IP was success.更多还原