【作者】 郝乐；

【导师】 李哲英；

【作者基本信息】 北京交通大学 ， 微电子学与固体电子学， 2008， 硕士

【摘要】 随着微电子技术的迅速发展,尤其是数字计算和信号处理技术的广泛应用,用数字电路处理模拟信号的情况日益普遍。所以模拟信号数字化是信息技术的发展趋势,而模数转换器在其中扮演着重要的角色。逐次逼近式A/D转换器,适用于分辨率要求为8～16位的A/D转换器,是采样率低于5Msps的中等至高等分辨率应用的常见结构,具有低功耗、小尺寸的特点。这些特点使其具有很宽的应用范围,例如便携/电池供电仪表、笔输入量化器、工业控制和数据/信号采集器等。本文设计了工作在1.8V单电源电压下,中速低功耗的12bit逐次逼近式A/D转换器。本文主要研究了A/D转换器中包括采样保持电路、D/A转换器、电容阵列和数字逻辑与时序控制等模块的设计,未研究的比较器模块由同组其它成员完成。为了提高A/D转换的精度,本设计采用全差分和下极板采样技术克服电荷注入效应和时钟馈通效应的影响。同时将采样电容嵌入到D/A转换电容阵列中,采用并行模数转换器分辨率的扩展结构,既保证了采样电容的采样精度值,又有效节省了芯片面积。在电容阵列的设计中,利用单位电容并联的方法减小金属MIM电容值的失配误差,并通过共质心版图布局,进一步提高转换精度。在数字控制模块的电路实现中,用基于环形计数器和移位寄存器的结构设计了逐次逼近逻辑电路。在整体版图设计时采用数模混合信号(AMS)的设计流程,即在一个芯片的设计时采用多种不同的方法,针对规范性强的数字部分采用定制设计方法中的标准单元法进行设计,对于那些严重影响性能的模拟部分采用全定制法进行设计,以求缩短设计周期,提高性能和芯片面积利用率。本次SAR ADC设计采用的是IBM 0.18μm DP6M CMOS7RF混合信号设计工艺。设计采用MOSIS公司提供的MPW(Multi-Project Wafer)方案流片,所以同一版图中还包括8-bit CPU设计和100MHz低噪声电荷泵锁相环频率合成器的设计。其中SAR ADC版图面积为172.03μm×317.92μm,MPW整体版图面积为1804μm×1804μm。完成版图后对整体电路进行仿真,设计满足12位SAR ADC的基本要求,逐次逼近ADC可以正常的工作。更多还原

【Abstract】 With high-speed development of microelectronic technology, especially the increasing use of digital computing and signal processing technology in applications, it is becoming common to deal with analog signal with digital circuits. So digitalizing analog signal is the trend of information technology, in which Analog to Digital converter plays an important role. Successive approximation (SAR) A/D converters are frequently the architecture of choice for medium-to-high-resolution applications with sample rates under 5 Mega samples per second (Msps). Because of providing low power consumption as well as a small form factor, SAR A/D converters have a wide variety of applications, such as portable/battery-powered instrument, pen digitizers, industrial controls and data/signal acquisition.In this paper, a 12-bit low power SAR A/D converter with medium speed is designed, which can work under a 1.8V power supply. This paper mainly focuses on several parts: S/H circuit, D/A converters, capacitance array and digital logic control in time sequence. Other group member completed the design of comparator.This design uses the difference technique and bottom sampling technique to overcome the charge injection effect and the clock feed-through effect. Improve the A/D converter accuracy at the same time, sampling capacitor embeds into the D/A converter capacitor array, takes the expansion of parallel structure to ensure the accuracy of conversion effectively and save the chip area. In the design of the capacitor array, it uses the unit’s method to reduce the mismatch error of the parallel MIM capacitance value, and adopts a whole concentric layout to increase conversion accuracy. In the digital control module of the circuit, design the successive approximation logic which based on the ring counter/shift register. In the overall layout design uses Mixed-signal (AMS) design flow, that is, in the design of digital part, uses the Full-Custom Design methodology based on the standard cell. In the analog part, uses the Full-Custom Design methodology, so as to shorten the design cycle and improve the performance and silicon available area.In the design, the SAR A/D converter is based on IBM 0.18um DP6M CMOS7RF mixed-signal design process, which uses the MPW (Multi-Project Wafer) to tape out by MOSIS. So in the same layout, there are also 8 - bit CPU design and low noise charge pump 100 MHz PLL Synthesizer Design. The layout area of the SAR ADC is , the MPW area is . After the completion of the layout on the whole circuit simulation, the simulation results show that the design meets 12 A/D converter requirements, the SAR A/D converter can work well.更多还原