基于H.264/AVC视频解码器的VLSI设计与研究

【作者】 郭志惠；

【导师】 杨兵；

【作者基本信息】 北方工业大学 ， 信号与信息处理， 2008， 硕士

【摘要】 H.264/AVC是ITU-T和MPEG组织共同推出的新一代视频压缩标准,其压缩效率较H.263和MPEG-4有显著提高。本文设计了一种适合H.264/AVC变字长解码器,提出了一种新的更快更高效适合解码的查表方法。在尽量减少时钟消耗和硬件开销的前提下,本文根据码流特点对解码模块结构进行了优化,使解码效率更优、时钟频率更高。解码控制电路中主要采用了桶型移位寄存器,并在解码过程中频繁使用了首一检测器。查表解码电路中,改变传统的遍历搜索比较的方法,本文根据码流的特点将码表按规律拆成多个子表,使查表效率和电路时序上有很大的突破,尤其标志符解码和非零系数值两个最难的解码模块有了突破性进展:标志符解码能够实现在两个时钟周期内完成,非零系数值解码在三个时钟周期内解出,并且该子模块电路能达到220M。同时考虑到IP可重复性设计和便于各器件移植,本文采用同步设计,外部接口都使用fifo公用接口。通过在Quart-usⅡ6.0 FPGA开发软件下仿真分析表明在该变长解码器能达到150M时钟频率,完全可以满足10M/S码率下H.264标准中Leve13.0的性能要求。论文的主要研究工作如下:1.研究变字长解码器的大规模集成电路设计和验证,主要包括静态时序分析、时序优化、布局布线、搭建测试平台,生成测试向量、编写参考模型等等验证和设计工作。2.研究变字长编解码算法,并根据协议设计了变字长解码器。同时在IP可重复性设计和可移植性方面做了研究,整个系统的设计使用Verilog硬件描述语言实现。3.解cavlc码中,本文根据码表的特点提出了一种新的查表方法,在不增加存储资源的条件下,通过优化结构提高解码效率,节省时钟周期,通过改变关键时序路径提高时钟频率。4.指数哥伦布解码过程中,本文优化解码器结构,减少解码所需要的时钟周期。更多还原

【Abstract】 H.264/AVC is a new video coding standard with enhanced higher compression than H.263 and MPEG raised by ITU-T and MPEG orgnizations. This paper proposes an implementation of variable length decoder for H.264/AVC. While minimizing the use of clock cycles and hardware cost, the design is separated into several parts according to the specialty of the code stream. Bucket shift register is used to control circuit, and the first one detector is used in the process of decoding. In tabular decoding circuit, the design discards the traditional way which is the way of traversing search comparison. Instead, the table is devided into a number of sub-tables according to the feature of code streams. It makes tabular efficiency and circuit timing have great breakthroughs, especially in the total_coffe and no_zero level decode modules: the total_coffe module decode need only 2 cycles and the nozero level module decode need only 3 cycles, and the frequence of the modules is 220 Mhz.. By simulating with Quartus II 6.0, the results shows that its maximal working frequency is around 220 MHz and it could fulfill the required performance of H.264/AVC standard level 3.0.The main contents of this paper are as follows. Firstly, it is the presentation of the design and the verification of VLD decoder with VLSI, such as sythsis, fitter, STA, coding reference module and so on. Secondly, it is the introduction of video coding standard, the history of its development, and video codec theory, etc. Thirdly the protocal of H.264/AVC and the princinple about VLD CODEC is read and researched. Then it is the design of decode of VLD with Verilog. A new way of decoding the stream with faster speed and less cycle is used. At the same time we use IP reused design for tansplanting between different devices, so we use general FIFO interface with others. According the feature of code, a new way of looking for table is used when decoding cavlc. Concretely speaking, the original table is devided into many sub-tables. In this way the speed of circuit is higher and decode in less cycle. At the same time we optimised the archtecture of circuit to improve the speed of circuit. In the last part, the clock cycle of decoding is reduced, and the structure of decoder is optimized.更多还原