【作者】 刘江林；

【导师】 杨景常；

【作者基本信息】 西华大学 ， 电力系统及其自动化， 2008， 硕士

【摘要】 在电子设计领域,随着计算机技术、大规模集成电路技术、EDA(ElectronicsDesign Automation)技术的发展和可编程逻辑器件的广泛应用,传统的自下而上的数字电路设计方法、工具、器件已远远落后于当今技术的发展。基于EDA技术和硬件描述语言(VHDL)的自上而下的设计技术正在承担起越来越多的数字系统设计任务。本课题的时间继电器智能测试仪的设计就是采用自上向下的设计方法,用单片机作为系统的主要控制部件,实现对整个电路的测试信号控制、数据运算处理、键盘扫描和控制液晶显示器(LCD)的显示输出等。以一块现场可编程逻辑器件FPGA(Field Programmable Gate Array)芯片(ACEX 1K30),完成测时间继电器/测频、基准频率分频、时序逻辑控制、计数、输出等功能。在QuartusⅡ平台上,用VHDL语言编程完成了FPGA的软件设计、编译、调试、仿真和下载。当选择测时间继电器时,在AT89S52单片机控制下给出一个启动信号,由时间继电器信号控制的闸门信号打开,同时时间继电器的信号和时间基准信号分别被送入计数器的输入端开始计数,当闸门信号关闭时计数器都同步停止计数,单片机将FPGA内的12位十进制计数器的计数值读入其内存进行处理后,并将计数结果送LCD显示。通过对本地键盘或远地可程控面板操作,可以分别对测时间继电器/测频率进行控制,同时也可以对计数器的开启、停止计数功能进行控制,也可以对各个计数器进行初始化。该系统除了能够测量时间继电器时间段外,还可以测试信号的频率等。AT89S52单片机内含256字节RAM和8K字节快闪存储器,因此全部控制程序可装入单片机。系统将单片机的控制灵活性及FPGA芯片(ACEX1K30)的现场可编程性相结合,不仅大大缩短了开发研制周期、降低了设计成本,而且使本系统具有结构紧凑、体积小、重量轻、可靠性高,测量时间/频率范围宽、测量精度高等优点。填补了我军某型航空时间继电器智能测试仪的空白,具有较高的经济价值和军事价值。本文详细论述了系统各部分硬件电路组成,单片机和FPGA的软件编程设计以及自上而下的设计方法。更多还原

【Abstract】 In the electronic field, along with the development of the computer technique, large scale integrate circuit technique and EDA (Electronics Design Automation) technique and aboard application of programmable logic device, traditional design methodology of digital circuit adopting bottom_up, tolls, devices has already dropped behind the development of the popular technique. Design technique adopting top_down are taking on more tasks of digital system design. The smart time relay meter design in this paper which adopts top_down design methodology uses the AT89S52 single chip computer as the main controlling parts. The AT89S52 single chip computer realizes test signal control, keyboard scan and output display of LCD. A FPGA (Field Programmable Gate Array) chip (ACEX 1K30) fulfills measuring time relay/measuring frequency, dividing frequency of time reference, timing logic control, count and output function. Under the flat of Quartus II, FPGA software designing, compiling, debugging, simulation and down are been carried out in VHDL(Very High Speed Integrated Circuit Hardware Description Language) language. A start signal is given under the controlling of AT89S52. when the choice of measuring time relay, strobe signal opens under the controlling of the time relay signal, the time relay signal and the bade time signals were sent to base counter input counting began at the same time, when the gates closed at the counter signals are synchronized to stop counting, the single chip computer would read 12 metric counting data to his memory in FPGA then process the counting data, and the last sent the results of the counting data to LCD display. Through the local keyboard or remote operation panel can be programmed, respectively measuring time relay / measuring frequency control, but also to counter the open, and stop counting functions of control, the various counters can also be initialized. In addition the system not only can test time of the time relay, but also can test the signal frequency. The single chip computer of AT89S52 includes 256 bytes of RAM and 8 K bytes of flash memory, so all controlling program can be downloads to the single chip computer. The system combines the controlling flexibility of single chip computer with programmable performance of FPGA chip (ACEX 1K30), so it can not only greatly shorten developed cycle, reducing the design costs, but also enable the system is compact, small size, weight light, high reliability measurement of time / frequency range wide, high precision advantages. It fills the blank of a certain type time relay of test for the smart instrument in my air force. It has a high economic and military value. This paper discusses in detail the different parts of the system hardware circuit, single chip computer, FPGA design, software programming and top-down design methods and so on.更多还原