【作者】 程钰涵；

【导师】 胡燕翔；

【作者基本信息】 天津师范大学 ， 教育技术学， 2008， 硕士

【摘要】 离散余弦变换(DCT)在图像编解码方面具有十分广泛的应用,目前已被JPEG、MPEG1、MPEG2、MPEG4和H26x等众多国际标准所采用。但由于其计算量较大,用软件实现难以满足实时处理的要求,对一些处理速度要求很高的地方,一般采用硬件设计的DCT处理电路。本文的主要研究内容为针对图像处理应用的8×8二维DCT离散余弦变换IP处理核的硬件实现的若干问题。本文首先介绍了DCT在图像处理中的作用和原理,以及利用DCT变换实现图像压缩的过程,并与其它变换比较体现了用DCT变换实现图像压缩的优势。然后对DCT的各种快速算法进行了分析研究,总结了前人对DCT快速算法及其VLSI实现的各种方法的优缺点,进而提出了一种DCT IP核的设计方案。该方案利用DCT的行列分离特性,采用6级流水线设计技术,将二维DCT转化为两个一维DCT。在一维DCT设计中,利用DCT余弦因子的对称性以及可旋转性,采用移位和加法逻辑来实现乘法运算,从而避免了采用乘法器设计所造成的资源和面积的浪费,提高运算速度。最后,对所设计的DCT处理核进行了综合和仿真验证,结果表明所设计的DCT处理核能够在100M时钟频率下能正确完成8×8DCT的逻辑运算。更多还原

【Abstract】 Discrete Cosine Transform is wildly used in coding and decoding of image processing, which has been used by many international standards such as JPEG, MPEG1, MPEG 2, MPEG 4, H26X and so forth. Because of its high computing, software can not meet with the requirement of real time process. Therefore, we advise adopting DCT process circuit to satisfy with the requirement of the speed for processing, due to strict circumstance. The content of this thesis is that 8*8 DCT IP code for hardware implementation.This thesis introduce the role and principle of discrete cosine transform DCT and briefly elaborate the process the image transform using DCT method, and then comprise with other transform to specify advantages for image transform using DCT transform. Furthermore, it specifies different DCT method, and then summarizes DCT high speed algorithm and the characteristics for VLSI implementation. According to characteristics of image process and IP design idea, DCT algorithm and hardwire implementation, this thesis introduce one DCT hardwire design to increase speed and minimize design areas and power.In this method, we adopt DCT column-row character, using 6 pipelines design, then transform 2-DCT into 1-DCT, column and row method. In 1-dct design, we use DCT cosine coefficients and by making use of its rotation characteristic, multiplication function can be designed by shift and addition logic instead of direct multiplication unit by which can save design resources while improve the speed. At last, synthesize and verification for design has been done. The result shown that the design could complete the function of 8×8DCT under 100M clock frequency.更多还原