【作者】 郭慧晶；

【导师】 陈辉煌； 周剑扬；

【作者基本信息】 厦门大学 ， 无线电物理， 2007， 硕士

【摘要】 当代超大规模集成电路设计日趋成熟,集成电路产业已经成为现代工业发展的基石,已经被广泛的应用到计算机、通讯、互联网、制造业等。当工艺发展到深亚微米的时候,功耗对电路的影响已经成为集成电路设计中的不可忽略的问题。功耗不但直接影响芯片的封装形式和成本,而且过高的功耗将导致芯片热量的增加,直接影响着芯片的可靠性。同时片上系统的设计是集成电路工艺提高的必然结果。对电路的性能、功耗、成本和可靠性都非常有利,已经成为集成电路发展的方向。但由于门数较多,功耗也就成为一个设计中的瓶颈问题。无线接入SOC芯片是无线自组织网的节点芯片,无线传感网络的上层协议采用的是基于IEEE802.15.4自行开发的协议,主要是针对低功耗、低速率的应用,数据传输速率在100Kps左右。本文研究了该芯片从逻辑综合到物理实现各个阶段的低功耗设计及其实施方法,为芯片的低功耗设计提供了方法和流程上的参考。该设计在芯片中均获得了有效的验证,可以应用在其它芯片设计中。为其它的芯片设计奠定基础。全文首先详细阐述了低功耗设计技术的发展状况以及研究意义,接下来具体分析了功耗的组成,以及在逻辑设计阶段动态功耗和静态功耗的优化方法。论文以无线接入SOC芯片为例,基于Cadence的EDA平台,对无线接入SOC芯片在逻辑综合阶段进行了低功耗的优化,主要采用的是门控时钟方法,并比较了优化结果;同时对无线接入SOC芯片的完成了后端设计,并对于物理实现的每个过程中的功耗优化策略进行了详细研究。在布局阶段:通过不断分析比较得到了最佳功耗布局方案;在时钟树生成阶段:采用多种功耗优化方法实现了低功耗设计。论文最后分析了深亚微米工艺条件下电源完整性问题,并进行了物理验证,以及问题的修复。更多还原

【Abstract】 In the present ages, the development of VLSI design is tend to be mature, IC industry has become the footstone of the development of modern industry, It has been broad applied to computer, communication, internet and manufacturing. When the process grow to deep sub micron, power could not be ignored in IC design., it not only effect the package and cost, but also lead to the too much heat, which directly effect chip reliability. SOC design is the result of IC development. It’s helpful for the circuit performance, power, cost and reliability, which has become to the direction of IC development. But with area growing, power has become to the key problem of IC design.Wireless access SOC chip is Wireless access chip, higher-layer protocol is based on the IEEE802.15.4 own develop protocol, mostly based on low power, low speed application, transmission speed is about 100Kps. This paper describes concept and methods of the implement of low power design of WirelessChip from logic synthesis to physical design, which provide a reference of implement method and flow. It can apply to other chip design to the basic of other chip design.This paper first provide an overview of low power technology development and research signification; then discusses the power distribution and optimization of all level. presents the method of low power synthesis of WirelessChip;.Based on Cadence EDA platform, implemented logic design and emphasized clock tree synthesis of low power, implemented low power physical design, floorplan phase adopt many methods for a better result, cts phase applied many ways to implemented low power design. At last this paper analyzed the power and physical verification problem of deep-sub micron process.更多还原