【作者】 付宏博；

【导师】 曹健；

【作者基本信息】 上海交通大学 ， 计算机应用技术， 2007， 硕士

【摘要】 船载航行数据记录仪VDR(Voyage Data Recorder)是记录船舶航行时各种参数的重要设备,这些数据可以为分析海难的原因提供重要的支持。目前的VDR设备,采用都是嵌入式工控机+各种板卡的方式,虽然集成度比较高,但是灵活性差、不容易升级,更重要的是后期维护比较困难。针对这种情况,本文提出了一种基于以太网架构的VDR系统,将图象卡、声音卡、数据采集卡、存储单元、主控单元等都各自封装在基于以太网接口的模块中,通过网络实现信息的采集、传输和存储。由于各个模块具有很大的独立性,只要接口之间的协议不变,某个模块的技术升级就不会影响到其它模块,由于采用了网络接口,实施时就可以根据船舶上的情况动态的增减模块,灵活性很高,如果发生故障可以对模块进行单独诊断,能迅速的定位故障点,不需要专业的工程师就可以实现模块的更换。本文在对国际海事组织以及中国等有关VDR标准分析的基础上,提出了系统的设计方案,对每个模块的功能做了定义,并对其中的3个模块:航行数据采集盒、主控制盒、雷达图象采集盒进行了具体的设计和实现。在航行数据采集盒的设计方面,根据该模块的特点,运用了SOPC(System On Programmable Chip)技术,在FPGA(Field Programmable Gate Array)中嵌入了Nios处理器软核,结合实时高效的嵌入式系统微内核uC/OS II以及轻量级的TCP/IP协议栈LwIP(Light weight IP)完成了系统的功能设计。其中对SOPC及其开发流程做了详细的论述,研究了需要采集的航行数据的种类和特点,设计了合理的任务和处理流程。在主控盒的设计方面,运用了当前比较流行的ARM(Advanced RISC Machines)技术,结合功能强大的uClinux操作系统实现了需求的功能。其中对ARM技术做了比较详细的论述,对S3C44B0X的外围接口电路、uClinux在S3C44B0X上的移植以及uClinux下的存储技术设备MTD(Memory Technology Device)驱动作了研究。在雷达图象采集盒的设计方面,根据雷达图象数据量大、点频高但采集频率低的特点,提出了用FPGA作为采集控制,用ARM做后期处理的方案。其中对雷达图象采集的难点做了详细的分析,对AD转换输出的时钟与ARM总线频率之间如何同步的问题做了深入的研究,并提出了用两个异步先进先出队列FIF(OFirst Input First Output)实现的方法。在完成方案设计的基础上给出了每个模块的具体实现并进行了相应的测试,以验证设计是否合理。测试结果表明,系统的功能达到了设计的要求。本文的意义在于,不仅成功的实现了一个全新架构的、性能优越的VDR系统,而且在系统的设计与开发中所采用的一些设计技术和方法具有很强的通用性,稍加改动就可以应用到其它领域。更多还原

【Abstract】 Voyage Data Recorder (VDR) is one important device which is used to record various parameters during the ship navigation. These data are very important support to analyze marine disaster reason. Current VDR device adopts built-in industrial control PCB board and various board cards. It has high integration level. But its flexibility is low and not easy to upgrade. Most important, it is not easy for later stage repair and maintenance. Based on this situation, this article has come up with one VDR system based on Ethernet infrastructure. Package image card, sound card, data acquisition card, storage unit and main control unit into modules based Ethernet network interface. It realizes information acquisition, transmission and storage via network. Each module has high level independency. If the communication protocol between interfaces is not changed, one module technology updating will not have impact on other modules. It adopts network interface. During implementation, it can increase or reduce modules based on ship dynamic situation. It has high level flexibility. If there is any fault, we can do single diagnosis for single module. It can orient the fault point very fast. So it does not need to have professional engineer to replace modules.Based on IMO and China relevant VDR standard analysis, we come up with system design scheme. We define each module’s function. At the same time, we have made detailed design and implementation for three modules which include navigation data acquisition box, main control box and radar image acquisition box.Concerning navigation data acquisition box design, based on this module characteristics, adopts SOPC technology, imbedded Nios server soft core into FPGA, combined with real time high efficient uC/OA II imbedded system micro-inner core and small TCP/IP protocol stack, it completes system function. Concerning SOPC and development process, it has made detailed discussion. It has investigated acquisition-required navigation data type and characteristics and designed reasonable task and processing flow.Concerning main control box design, it adopts up-to-date ARM technology and combines powerful uClinux operation system to realize wanted functions. It has made detailed discussion of ARM technology. It has made investigation of S3C44BOX peripheral interface circuit, uClinux transplantation on S3C44BOX and MTD device driving under uClinux.Concerning radar image acquisition box design, based on radar image data large amount, high point frequency and low level acquisition frequency, it comes up with the scheme which uses FPGA as acquisition control and use ARM as later stage disposal. It has made detailed analysis on radar image acquisition difficulty. It has made deep investigation of the problem of the synchronization of AD conversion output clock and ARM bus frequency. And it comes up with using 2 asynchronous FIFO realization method.After every module being validated independently, the entire system is tested synthetically.The result indicated that the system function is satified the designed requirements.This article is not only successful to come up with one new infrastructure and functional dvantage VDR system. At the same time, various modules’design technology and method just need to be modified in small part, then they can be applied to other areas. It has powerful versatility.更多还原