【作者】 商世伟；

【导师】 徐昌庆； 王伟；

【作者基本信息】 上海交通大学 ， 电子与通信工程， 2007， 硕士

【摘要】 近年来随着电子系统朝着大规模、小体积、高速度的方向不断发展,基于传统的电路设计理论设计出来的电路越来越多的遇到了诸如信号完整性和电源完整性之类的问题,严重的甚至会导致系统无法工作。要适应当前电子系统的发展,光靠设计完成后的修修补补是远远不能解决问题的,而且成品后期解决问题耗费的成本,要数百倍于产品设计阶段解决问题的成本,必须从设计阶段就应用一整套的高速电路设计理论来指导电路板的设计。在这样的背景下,各种各样的高速电路设计理论应运而生。高速电路首先要解决信号完整性问题。本文在理想的无损传输线的基础上,利用传输线理论,分析研究高速印刷电路板走线的信号特性,发现影响信号完整性的原因并找出解决常用的几种解决方法及各方法的优缺点。其中特意介绍了一种格形图的方法对信号的波形进行推算,并将推算波形和仿真波形进行对比。基于实际的有损传输线,本文还进一步研究了高速信号的传输特性,分析了直流损耗、趋肤效应,并且研究了PCB布线中常用的蛇行线、直角走线的影响。数字电路系统中普遍存在着串扰,这种串扰也存在于芯片内部、封装,PCB板内、板间,连接器、线缆间等。通过对板级串扰产生的原因及串扰对传输时间和信号完整性的影响研究,可以找到两种终端匹配方法有效抑制串扰的影响。电源完整性是高速电路板级设计需要注意的另一个方面,它可分为电源系统完整性、返回路径(通常是非理想的)和同步开关噪声三个密切相关的问题。本文依次分析了这三个问题,并给出了解决这三个问题的指导性意见。更多还原

【Abstract】 In recent years,advances in photolithography and IC manufacturing technology, which drive Moore’s Law, means the features sizes on-chip will always decrease. This has an important impact. As the gate channel length decrease, the switching time of each gate will decrease. Shorter switching time means shorter rise time for the output drivers and higher clock frequencies possible. Nearly all signal integrity and power integrity problems get worse with shorter rise time. In the worst situation, these problems may lead to system collapse.When we entered the 21st century, we entered a new era for electronic products. Shrinking design cycle times means the product must work the first time. We do not have the luxury of multiple build-it, test-it, re-design-it loops. If signal integrity and power integrity effects are not taken into account right at the beginning and designed out, products will fail. Many kinds of high-speed circuit design theories come into being in this background.The theory of transmission line with no resistive losses is the base of high-speed circuit design in board-level. Signal characteristics must be analyzed in high-speed PCBs. And the reasons to effect signal integrity problems, the methods to solve them are also researched at the very start. Crosstalk exists in digital circuits extensively. That how digital times and signal integrity are influenced by crosstalk and the methods to reduce the crosstalk is discussed in the nest charter. In reality, there are DC losses, dielectric losses, and skin effect in nonideal transmission lines. These nonideal factors are analyzed in charter 4. Power integrity is another important problem in high-speed circuit design area. The effects such as system integrity, simultaneous switching noise and nonideal current return path that can devastate a digital design are researched in the last charter.更多还原